Energy consumption has become a critical design issue in real-time embedded systems (RTES), which are prevalent in many applications such as automobiles, consumer electronics, etc. RTES normally consist of a single-core or multi-cores structures for running various applications. For multi-core structures, Network-on-Chip (NoC) communication architectures have emerged as a promising solution to address the inter-cores communication using a micro-network. In this work, we investigated the relationship between the real-time applications and the general low energy design techniques. In particular, we looked at the following areas: Exploiting dynamic workload variation for energy reduction in real-time systems, optimal link scheduling on improving best-effort and guaranteed services performa...[ Read more ]

Energy consumption has become a critical design issue in real-time embedded systems (RTES), which are prevalent in many applications such as automobiles, consumer electronics, etc. RTES normally consist of a single-core or multi-cores structures for running various applications. For multi-core structures, Network-on-Chip (NoC) communication architectures have emerged as a promising solution to address the inter-cores communication using a micro-network. In this work, we investigated the relationship between the real-time applications and the general low energy design techniques. In particular, we looked at the following areas: Exploiting dynamic workload variation for energy reduction in real-time systems, optimal link scheduling on improving best-effort and guaranteed services performance in NoC, energy-efficient NoC synthesis considering voltage islands partitioning.

First, we propose a novel energy reduction strategy for the offline variable voltage task scheduling of both preemptive and non-preemptive systems. During the construction of the static voltage schedule, instead of assuming all tasks are running at the worst-case workload, run-time workload variations are considered. This work can be viewed as an interaction between the offline voltage scheduling and the online dynamic voltage scaling.

Next, we shift our focus on the communication network of the multi-cores systems. For applications with hard deadline, guaranteed services (GS) are required to satisfy the deadline requirement. GS applications always complement the Best-Effort services (BE) to increase the resources utilization efficiency. In this thesis, an approach based on optimal link scheduling is proposed to minimize the network resources utilization for guaranteed services applications. In addition, we propose a novel router architecture using a shared-buffer implementation scheme to further reduce the network resources utilization.

Another area of work with regards to low energy design is the NoC system synthesis and voltage islands partitioning. In order to reduce the complexity of the power supply network and to minimize the number of level shifters required, voltage islands concept was proposed for core-based System-on-Chip (SoC) systems. Here the chip is powered by several voltage sources and each voltage source powers a portion of the entire chip which is called the voltage islands. The design flow of the NoC-based multiprocessor RTES considering voltage islands is very complicated and involves several interacting steps. In this work, we study different optimization techniques for the NoC system synthesis and proposed an integrated framework for NoC synthesis targeted for low energy consumption design.