Because of its high carrier mobility, polycrystalline silicon (poly-Si) thin-film transistor (TFT) is actively being deployed in mobile devices requiring high-resolution or highly integrated active-matrix flat-panel displays. However, both the low-resistance metal gate lines for reducing the signal delay along a scan line and the inexpensive glass substrates used in such displays impose a ceiling on the processing temperature. One consequence of this is reduced dopant activation efficiency, resulting in a high source/drain parasitic series resistance that may mask the intrinsic performance of a TFT. This thesis focuses on the proposal and demonstration of new fabrication technologies for the realization of low-temperature poly-Si TFTs with low parasitic resistance....[ Read more ]

Because of its high carrier mobility, polycrystalline silicon (poly-Si) thin-film transistor (TFT) is actively being deployed in mobile devices requiring high-resolution or highly integrated active-matrix flat-panel displays. However, both the low-resistance metal gate lines for reducing the signal delay along a scan line and the inexpensive glass substrates used in such displays impose a ceiling on the processing temperature. One consequence of this is reduced dopant activation efficiency, resulting in a high source/drain parasitic series resistance that may mask the intrinsic performance of a TFT. This thesis focuses on the proposal and demonstration of new fabrication technologies for the realization of low-temperature poly-Si TFTs with low parasitic resistance.

Replacement of conventional poly-Si source and drain with aluminum (Al) using a structure of a titanium (Ti) on Al stack contacting the poly-Si in the source and drain regions of a TFT through lithographically defined replacement windows is firstly proposed. The resistivity of the replacement Al is measured to be ~7μΩ.cm, which is much lower than that of p-type poly-Si, ~3,150μΩ.cm, and that of n-type poly-Si, 17,800 μΩ.cm. With partial replacement of the source/drain poly-Si with Al, ~20% and ~50% improvement in the effective field-effect mobility of p- and n-type poly-Si TFTs are achieved, respectively.

Poly-Si TFTs with metal gate, source and drain have also been successfully demonstrated. During the fabrication of such p-type TFTs, no deliberate dopant implantation and activation steps are needed such that the fabrication process is much simplified. N-type TFTs can also be fabricated if n-type dopant is implanted before the replacement heat-treatment. The low-resistance metal gate is very useful for the reduction of signal delay along it in large-area active-matrix displays, and the metal source and drain reduce the parasitic resistance for the recovery of the intrinsic performance of a TFT.

During the fabrication of poly-Si TFTs with Al fully replaced source and drain, Al, which is an acceptor in silicon, will diffuse into the channel poly-Si. Its effects on the TFT performance are investigated. It is found that poly-Si TFTs with Al replaced source and drain showed steeper sub-threshold slope, reduced threshold voltage, increased field-effect mobility and immunity to short channel effects. Such improvements are attributed to the passivation effects of Al.

Aluminum-induced crystallization (AIC) is also proposed as a technique to realize TFTs with self-aligned metal electrodes (SAME). The poly-Si in the source and drain regions up to the edges of the channel is converted to amorphous silicon by ion implantation. Self-alignment is achieved using the gate electrode as the implant mask. AIC of the amorphized source and drain regions is subsequently carried out, resulting in a replacement of the Si in the source and drain regions by Al. Since the entire length of the channel region under the gate electrode is not amorphized, the replacement is self-aligned and the penetration of the replacement Al into the channel region is prevented. SAME poly-Si TFT with channel length down to 1μm has been realized and characterized.