The ultra thin body (UTB) double gate (DG) MOSFET is believed to be the most promising device candidate as the CMOS technology scales down to nanometer regime due to its excellent suppression of short channel effect (SCE). For the circuit design purpose, it is important to develop an accurate and fast compact model of the UTB DG MOSFETs. Meanwhile, although the development of UTB DG MOSFET technology is mostly driven by the downscaling of digital CMOS circuits, the analog/RF performances of UTB DG MOSFETs has become an interesting research topic. This is mainly because of the motivation to integrate an entire system into a single chip or so-called system-on-chip design approach....[ Read more ]

The ultra thin body (UTB) double gate (DG) MOSFET is believed to be the most promising device candidate as the CMOS technology scales down to nanometer regime due to its excellent suppression of short channel effect (SCE). For the circuit design purpose, it is important to develop an accurate and fast compact model of the UTB DG MOSFETs. Meanwhile, although the development of UTB DG MOSFET technology is mostly driven by the downscaling of digital CMOS circuits, the analog/RF performances of UTB DG MOSFETs has become an interesting research topic. This is mainly because of the motivation to integrate an entire system into a single chip or so-called system-on-chip design approach.

The compact modeling of two types of UTB DG MOSFETs are discussed. The symmetric DG MOSFET (SDG) is the most conventional structure with the connected gates, whereas the Multiple Independent Gate FET (MIGFET) is featured by the separated front and back gates. The implicit modeling based on the iteration algorithm has been reported before and its correctness has been justified by comparisons to the 2-D numerical simulation, but the implicit model requires extensive computation. Another issue for the implicit modeling is the convergence. To solve these problems, we develop a non-iteration based compact model. The compact model is based on an approximation algorithm and correction terms and is more suitable for the circuit simulation. Its accuracy is verified by comparison to the implicit solution and the numerical simulation. The current model and some non-ideal factors are also included.

A trimming technique and chemical-mechanical-polishing method was used to fabricate MIGFET devices on SOI substrates. The trimming method was used to fabricate the fin body thickness less than 100nm. The top and bottom gates are separated using the chemical mechanical polishing (CMP). Various DC and RF characterizations are performed. We characterize the RF linearity of symmetric FinFETs and MIGFETs. The MIGFETs' linearity improvement through the optimized DC bias for each individual gate will be proposed. This feature may provide a new design alternative for the low power high linearity RF circuit.

The FinFET fin body thickness is crucial to device performance. A simple method to extract the fin body thickness using a reference device is developed. The extraction results show good agreement with the microscopic measurement results. The time domain and frequency domain methods are used to characterize the FinFET device noise performance. It is found that low-frequency noise performance has strong correlation with the fin body thickness. The noise performances under static and switching bias conditions are compared with the MIGFET devices.