Computed tomography (CT) is a primary non-invasive medical diagnostic modality. In a CT system, X-ray radiation is normally converted into visible light by a scintillator screen, which is further sensed by a solid-state imaging sensor. It requires a detecting sensor with wide dynamic range (WDR) and high speed. The existing industry is dominated by hybrid detector designs with amorphous silicon (α-Si) or charge-coupled device (CCD) photodiode array and CMOS acquisition circuits. Monolithic CMOS imaging sensor (CIS) has great potentials for CT detectors. This thesis focuses on exploring novel CMOS imaging sensor technologies for CT applications. The thesis first introduces the application of CT and various types of solid-state imaging sensors. Then, it analyzes existing wide dynamic rang...[ Read more ]

Computed tomography (CT) is a primary non-invasive medical diagnostic modality. In a CT system, X-ray radiation is normally converted into visible light by a scintillator screen, which is further sensed by a solid-state imaging sensor. It requires a detecting sensor with wide dynamic range (WDR) and high speed. The existing industry is dominated by hybrid detector designs with amorphous silicon (α-Si) or charge-coupled device (CCD) photodiode array and CMOS acquisition circuits. Monolithic CMOS imaging sensor (CIS) has great potentials for CT detectors. This thesis focuses on exploring novel CMOS imaging sensor technologies for CT applications. The thesis first introduces the application of CT and various types of solid-state imaging sensors. Then, it analyzes existing wide dynamic range CIS techniques and introduces our design of a WDR CIS with good linearity. The most important contribution of this thesis is that it continues to introduce our designs of CMOS imaging sensors for clinical CT and for micro-CT applications respectively.

Existing CMOS detectors for clinical CT are limited by their low linearity. They also need high-resolution external analog-to-digital converters (ADC) to quantize the WDR. In this thesis, a novel synchronous partial quantization technique is developed to enable monolithic digital CMOS CT detector. Improved from previous current quantization designs, the new detector quantizes the photocurrent in the charge domain with constant charge packet size. As the result, the detector can quantize the WDR photocurrent with improved linearity. The two-step charge-domain ADC scheme also allows low resolution single-slope ADCs for residual voltage quantization, which enables in-pixel integration. A prototype pixel detector is fabricated in a 0.35um CMOS process. Silicon measurements show the detector can quantize signal currents from 6 pA to 63.4 nA with relative gain deviation lower than 0.06% at 1.1k Hz frame rate, which does not generate detector-induced artifact after the image reconstruction. The detector noise is smaller than the X-ray Poisson noise in the whole signal range. The minimum detector noise is 0.8 pA_rms. Hence, the detector achieves 16.6 bits dynamic range. The geometrical detective efficiency (GDE) of the detector is 75.5% including the band-gap voltage reference and ADC. The digital pixel detector can be easily tiled into a 2D CT detection panel.

A high-speed CMOS imaging sensor is designed for a micro-CT scanner. The high-speed CIS normally has low optical sensitivity due to the short integration time. For applications, such as micro-CT, this is a major limitation. In this thesis, we developed a novel high-speed CIS with very high optical sensitivity. To maximize the sensitivity, we developed a capacitive trans-impedance amplifier (CTIA) pixel with a tiny metal-oxide-metal (MOM) capacitor. As a result, the noise is greatly reduced, while the optical sensitivity improves dramatically. We developed an on-chip calibration scheme with in-pixel circuits to compensate the mismatch across the pixel array in the digital domain. At the column-level, a successive-approximation (SAR) ADC is designed to achieve 10-bit resolution with small area. For testing modes, the column circuits are configured into a two-step ADC to provide 13-bit dynamic range. The design is fabricated in a 0.18um CMOS process. The 256×256 CIS samples up to 1500fps. The pixel integration capacitor is 0.7fF, which enables the optical sensitivity to be 68.5V/lux·s with white light illumination. This sensitivity is much better than benchmark high-speed CIS designs. The 1500fps CIS can capture recognizable images with illumination down to 1lux. The CIS temporal noise is 13.6e-. Pixel-level calibration suppresses the fixed-pattern noise lower than 0.52%. The prototype chip consumes 300mW power.