Low-dropout regulators (LDRs) are indispensible components widely used in system-on-chip (SoC) designs to power up noise-sensitive blocks. With the proliferation of portable applications, LDRs are required / desired to have accurate and fast regulation with low quiescent current consumption, compact chip area and without requiring any off-chip capacitors. This research focuses on the analysis and design of high-performance CMOS output-capacitor-free LDRs for SoC power management applications.

Firstly, output-capacitor-free adaptively biased LDR (AB LDR) topology is proposed with two implementations demonstrated. The AB LDRs, which combine techniques of advanced compensation and adaptive biasing, achieve accurate and fast regulation while keeping low quiescent current at light l...[ Read more ]

Low-dropout regulators (LDRs) are indispensible components widely used in system-on-chip (SoC) designs to power up noise-sensitive blocks. With the proliferation of portable applications, LDRs are required / desired to have accurate and fast regulation with low quiescent current consumption, compact chip area and without requiring any off-chip capacitors. This research focuses on the analysis and design of high-performance CMOS output-capacitor-free LDRs for SoC power management applications.

Firstly, output-capacitor-free adaptively biased LDR (AB LDR) topology is proposed with two implementations demonstrated. The AB LDRs, which combine techniques of advanced compensation and adaptive biasing, achieve accurate and fast regulation while keeping low quiescent current at light load and high current efficiency at heavy load, such that the long standby time and working time of the target application are neither compromised. Due to the multi-stage regulation, the power MOS is allowed to work in the linear region at heavy load to greatly save chip area while still maintaining a good regulation precision. With the extended loop UGF, the PSR is enhanced and the output impedance is reduced; faster transient responses in the heavy load region are also achieved. Stability of the AB LDRs is thoroughly analyzed, with the main feedback loop (MFL), the adaptive biasing loop (ABL), and the local stability of the load current sensors considered. Design trade-offs are considered and design strategies are suggested. The in-depth analysis on the stability of the symmetrically matched current-voltage mirror (SMCVM) used in the load current sensor is performed for the first time, showing why and how it can be stabilized by its internal parasitic capacitances, without any extra compensation cost. The analysis and design of the proposed AB LDRs are verified by extensive simulation and measurement results.

Secondly, adaptively biased LDR with sub-threshold undershoot reduction (ABSTUR LDR) is proposed. Due to the low biasing current at light load of an AB LDR, the worst-case load transient occurs when the load current steps up from the minimum level (e.g., 0μA) to the maximum level (e.g., 100mA) in a short time (e.g., 1μs). A dedicated low-voltage compatible and low-power consumption STUR circuit is introduced to reduce the undershoot voltage associated with the fast and large step-up of load current. Stability analysis of the ABSTUR LDR is comprehensively presented and, based on the analysis, design trade-off between undershoot-reduction strength and MFL stability is clarified and design strategy is then suggested. The proposed ABSTUR LDR maintains the advantages gained by the AB LDR, while significantly improves the worst-case load transient responses.

Finally, an LDR topology with low quiescent current and high PSR-bandwidth (LQC-HPSR LDR) based on cascoding is proposed for post-regulation of emerging high-frequency switching converters. Two preliminary examples of the proposed LQC-HPSR LDRs, namely, the 2T LQC-HPSR LDR and the 3T LQC-HPSR LDR are designed and fabricated. The measured full-load PSRs up to 50 MHz are better than -22.7dB and -37.5dB, respectively, while the quiescent current consumption are only 28.4 and 39.4 μA, respectively.