Integration of different circuits in a single chip is an unstoppable trend as the technology is being pushed forward. This enables more sophisticated functions to be embedded in a far smaller physical area. Power management circuits will definitely take an important part in this design revolution because a more demanding supply voltage quality is required by different signal blocks.

In this thesis, a converter and two different regulators with the emphasis on speed, power, noise interferences and silicon area will be discussed to accommodate the requirements for different points of load.

An output voltage ripple aware design for different voltage ramp signal of voltage-mode CCM random frequency buck converter for conductive EMI reduction is proposed to illustrate the effects o...[ Read more ]

Integration of different circuits in a single chip is an unstoppable trend as the technology is being pushed forward. This enables more sophisticated functions to be embedded in a far smaller physical area. Power management circuits will definitely take an important part in this design revolution because a more demanding supply voltage quality is required by different signal blocks.

In this thesis, a converter and two different regulators with the emphasis on speed, power, noise interferences and silicon area will be discussed to accommodate the requirements for different points of load.

An output voltage ripple aware design for different voltage ramp signal of voltage-mode CCM random frequency buck converter for conductive EMI reduction is proposed to illustrate the effects of pulse-width-modulation ramp signal on the output voltage ripple. A mathematical analysis has been carried out to model the output voltage ripple of a random switching frequency buck converter. Simulations of the converter have been undertaken and measured results from the converter, fabricated with a standard 0.35μm CMOS process, verify the proposed design approach. From experimental results, a carefully designed ramp can reduce the output voltage ripple by more than 8 times without significant influence on the inductor current spectrum spread and any increment on the output filtering inductance and capacitance compared to the conventional design.

An output capacitor-less low-dropout regulator for on chip application with active feedback and slew-rate enhancement circuit is presented. The feedback compensation scheme and transient response enhancement circuit have been modeled and experimentally verified in a standard 0.35μm CMOS process. The total compensation capacitance is limited to 7pF. From experimental results, the implemented regulator can operate from a supply voltage of 1.8V to 4.5V with a minimum dropout voltage of 0.2V at maximum 100mA load and total quiescent current of 20μA.

A wide loading range output capacitor-less low-dropout regulator with a Power Supply Rejection (PSR) boosting filter circuit for improving supply noise rejection at middle to high frequency is proposed. A model and experimental verification have been completed with a standard 0.13μm CMOS process. 1pF on-chip capacitance is delegated to stability compensation and 20pF capacitance is used for the PSR filter. From experimental results, the implemented regulator can operate with a supply voltage of 1.2V with a nominal dropout voltage of 0.2V at maximum 50mA load and total quiescent current of 37.32μA with 40dB power supply rejection at 1MHz across entire loading range.