GaN based high electron mobility transistors (HEMTs) technology has witnessed rapid development during the last decade in the applications of high-frequency power amplifiers, high-efficiency power switches and high temperature integrated circuits (ICs). Conventional AlGaN/GaN HEMTs are fabricated on the Ga-face C-plane epitaxial wafers with inherent strong spontaneous and piezoelectric polarization that yields high two-dimensional electron gas (2DEG) density. While the high 2DEG density consequently results in high current density, the channel is normally-on and requires a negative gate bias for pinch-off, presenting the device as depletion-mode (D-mode). However, in circuit applications, the enhancement-mode (E-mode) devices with positive threshold voltage are highly desirable...[ Read more ]

GaN based high electron mobility transistors (HEMTs) technology has witnessed rapid development during the last decade in the applications of high-frequency power amplifiers, high-efficiency power switches and high temperature integrated circuits (ICs). Conventional AlGaN/GaN HEMTs are fabricated on the Ga-face C-plane epitaxial wafers with inherent strong spontaneous and piezoelectric polarization that yields high two-dimensional electron gas (2DEG) density. While the high 2DEG density consequently results in high current density, the channel is normally-on and requires a negative gate bias for pinch-off, presenting the device as depletion-mode (D-mode). However, in circuit applications, the enhancement-mode (E-mode) devices with positive threshold voltage are highly desirable for the reduced circuit complexity and fail-safe operation. By replacing the D-mode devices with E-mode ones, the negative-polarity supply voltage can be eliminated from the power amplifier and power switch modules. The monolithic integration of E/D-mode HEMTs also allows the implementation of the direct-coupled FET logic (DCFL) integrated circuits that becomes the technology of choice for GaN digital ICs due to the lack of high-performance GaN p-channel devices. In general, E-mode operation of the GaN devices would deliver enhanced performance in circuit and system levels in RF, power, and mixed-signal applications.

The first part of this thesis presents a fabrication technology of E-mode AlGaN/GaN HEMTs using standard fluorine ion implantation equipment that is widely available in semiconductor micro-chip fabs. An 80 nm silicon nitride layer was deposited on the AlGaN as an energy-absorbing layer that slows down the high energy (~25 keV) fluorine ions so that majority of the fluorine ions are incorporated in the AlGaN barrier. The threshold voltage was successfully shifted from -1.9 V to +1.8 V, converting depletion mode HEMTs to enhancement-mode ones. The fluorine ion distribution profile was confirmed by Secondary Ion Mass Spectrometry (SIMS). The slowdown threshold voltage shift at positive region is revealed by the plasma ion implantation experiment and is explained by the location-dependent model. An insulator between gate and AlGaN can be used to increase the efficiency of threshold voltage shift modulated by fluorine ions.

The second part of this thesis focuses on investigating the underlying device physics (especially the drain induced barrier lowering (DIBL) effect) in a new metal-2DEG tunnel junction FETs (TJFETs) by numerical simulation. It is found that although the 2DEG channel of TJFETs is “ON” at OFF-state, the drain influence on the source Schottky tunneling junction is blocked well at high drain bias due to the pinch-off at the drain-side gate edge of a TJFET with relatively long channel. The short channel TJFETs show a weaker dependence of DIBL effect on the buffer compensation doping than the conventional metal-insulator-semiconductor high electron mobility transistors (MISHEMTs), because the DIBL effect in TJFETs is mainly suppressed by the source Schottky junction. Even with zero compensation doping, short channel TJFETs exhibit relatively small DIBL effect (e.g. 166mV/V for L_g = 100 nm). The gate capacitance partitioning in the AlGaN/GaN TJFETs is investigated by both numerical simulation and experimental characterizations. Representative characteristics such as the gate-bias dependent parasitic resistance and the gate induced barrier lowering effect of the Schottky tunnel junctions are identified. The gate capacitance partitioning behavior in TJFETs is explained by the gate induced source Schottky barrier lowering effect. The results from this work provide valuable design guidelines for performance optimization in TJFETs.