The critical dimensions of semiconductor devices are miniaturized with complementary metal-oxide-semiconductor (CMOS) technology scaling. Increasing numbers of transistors are crammed onto integrated circuits, thereby enhancing the operating frequency and functionality. The power consumption of integrated circuits increases with larger number of transistors and higher operating frequency. Excessive power consumption is a primary hindrance to the advancement of CMOS integrated circuits. Leakage currents are important sources of power consumption in modern nanoscale CMOS integrated circuits. Suppressing subthreshold leakage currents in large scale integrated circuits is essential for achieving green computing and facilitating the proliferation of portable electronics....[ Read more ]

The critical dimensions of semiconductor devices are miniaturized with complementary metal-oxide-semiconductor (CMOS) technology scaling. Increasing numbers of transistors are crammed onto integrated circuits, thereby enhancing the operating frequency and functionality. The power consumption of integrated circuits increases with larger number of transistors and higher operating frequency. Excessive power consumption is a primary hindrance to the advancement of CMOS integrated circuits. Leakage currents are important sources of power consumption in modern nanoscale CMOS integrated circuits. Suppressing subthreshold leakage currents in large scale integrated circuits is essential for achieving green computing and facilitating the proliferation of portable electronics.

Multi-threshold CMOS (MTCMOS), which is also known as power/ground gating, is the most commonly used leakage power suppression technique in state-of-the-art integrated circuits. Significant power and ground distribution network noise is produced when an MTCMOS circuit block transitions from sleep mode to active mode. Mode transition noise is the most important reliability issue in MTCMOS circuits. The generation mechanisms of mode transition noise in MTCMOS circuits are explored in this dissertation. The effectiveness of different noise-aware combinational MTCMOS circuit techniques to deal with the mode transition noise phenomenon is evaluated. An intermediate relaxation mode is investigated to gradually dump the charge stored on the virtual ground wire to the real ground distribution network during the sleep to active mode transitions. Novel noise-aware sequential MTCMOS circuits are presented. A low-leakage data retention sleep mode is implemented with smaller centralized sleep transistors to suppress the mode transition noise produced during the reactivation events in sequential MTCMOS circuits.

Threshold voltage tuning techniques are typically utilized for leakage power reduction or performance enhancement in integrated circuits. A new application of the threshold voltage tuning methodology is proposed to lower the reactivation noise with smaller sleep transistors and shorter reactivation delay in MTCMOS circuits. The principal mechanism of noise reduction and silicon area compaction in threshold voltage tuned MTCMOS circuits is investigated. Threshold voltage tuning is also effective in mitigating the reactivation noise in sequential MTCMOS circuits. A new dynamic forward body bias technique is presented to alleviate the mode transition noise in sequential MTCMOS circuits without sacrificing the data retention capability in low-leakage sleep mode.

Sleep signal slew rate modulation is an alternative technique that is effective for suppressing the reactivation noise in MTCMOS circuits. A triple-phase sleep signal slew rate modulation technique with a novel digital sleep signal generator is proposed in this dissertation. With the new digital triple-phase sleep signal slew rate modulation technique, fast and energy efficient mode transitions are achieved with negligible reactivation noise in MTCMOS circuits.

The leakage currents that are produced by on-chip memory increase the power consumption of high performance microprocessors. Furthermore, the data stability and write ability of static random-access memory (SRAM) cells are degraded with lower supply voltage, shrinking dimensions of transistors, and exacerbated process variations in each new CMOS technology generation. Compact, robust, and energy efficient memory design is pivotal in deeply scaled CMOS integrated circuits. The application of MTCMOS technique to SRAM circuits for leakage power suppression is investigated in this dissertation. Various novel asymmetrically ground-gated MTCMOS SRAM circuits are proposed for providing a low-leakage sleep mode with data retention capability. With the new asymmetrical power and ground gating techniques, the data stability is significantly enhanced during both read operations and idle status. Specialized write assist circuitry are also proposed to provide wider write voltage margins with the new memory cells.