CMOS image sensor technology is developing rapidly as the device feature size is continuously being scaled down according to Moore’s Law. With pixel resolution and data throughput aggressively increasing, low power is becoming a key requirement for future image sensor. One of the most power hungry building blocks in a CMOS image sensor is the Analog-to-digital converter (ADC). In order to strike the best trade-off between power and speed, we propose a hybrid ADC scheme by combing the single slope ADC and SAR ADC. As a result, the proposed hybrid ADC scheme can feature high energy efficiency due to the SAR architecture and a monolithic transfer function due to the single slope architecture. A mega-pixel image sensor is fabricated and tested based on the proposed hybrid ADC scheme...[ Read more ]

CMOS image sensor technology is developing rapidly as the device feature size is continuously being scaled down according to Moore’s Law. With pixel resolution and data throughput aggressively increasing, low power is becoming a key requirement for future image sensor. One of the most power hungry building blocks in a CMOS image sensor is the Analog-to-digital converter (ADC). In order to strike the best trade-off between power and speed, we propose a hybrid ADC scheme by combing the single slope ADC and SAR ADC. As a result, the proposed hybrid ADC scheme can feature high energy efficiency due to the SAR architecture and a monolithic transfer function due to the single slope architecture. A mega-pixel image sensor is fabricated and tested based on the proposed hybrid ADC scheme and deployed in a column-parallel architecture using 0.18 μm CMOS technology. Compared to previously reported mega-pixel imager, the proposed ADC scheme can reduce the power consumption by more than half. Compared to a 11-bit SAR ADC, the proposed hybrid solution can reduce the area by more than 50%.

Moreover, column-parallel sigma delta ADCs with both discrete time and continuous time are proposed and implemented in our work for low power CMOS image sensor applications. In the discrete time sigma delta ADC, an inverter is used to realize the switch capacitor modulator while in continuous time sigma delta ADC, a high resistance and metal-insulator-metal capacitor is used to implement the R-C integrator. In order to reduce power in the second stage of the continuous time sigma delta ADC, an inverter is used to replace the conventional differential amplifier. An implicit front-end variable gain amplifier (VGA) is achieved in the proposed ADC scheme, without consumes extra power and chip area.

The concept of low-power imager is pushed further by exploring energy harvesting capabilities targeting battery-free wireless camera network applications. In this work, we also propose an imager architecture with low power and energy harvesting capabilities implemented using 0.35 μm CMOS technology. The pixel in the proposed imager can be programmed into an imaging mode or energy harvesting mode. The quantization circuit is implemented using current-mode circuitry in order to reduce the voltage swing and improve the energy efficiency of the design. Experimental results illustrate promising avenues for self-powered wireless camera network applications.