The demand on high-speed CMOS image sensor (CIS) becomes higher in recent years. They are important for a wide range of applications, such as radiography, particle detection, sports, mechanical diagnosis, robot guidance, security surveillance and bio-medical research. High sensitivity is required in high-speed CISs as the exposure time is short. CISs with conventional pixels have low sensitivities due to the large photodiode capacitor. Image lag is evident with the traditional lateral charge transfer gate especially under low illumination. Also, the column parallel analog-to-digital converter (ADC) arrays in existing CISs have either low resolution or large area.

In this thesis, two CISs with capacitive transimpedance amplifier (CTIA) pixels are developed to enhance the imaging...[ Read more ]

The demand on high-speed CMOS image sensor (CIS) becomes higher in recent years. They are important for a wide range of applications, such as radiography, particle detection, sports, mechanical diagnosis, robot guidance, security surveillance and bio-medical research. High sensitivity is required in high-speed CISs as the exposure time is short. CISs with conventional pixels have low sensitivities due to the large photodiode capacitor. Image lag is evident with the traditional lateral charge transfer gate especially under low illumination. Also, the column parallel analog-to-digital converter (ADC) arrays in existing CISs have either low resolution or large area.

In this thesis, two CISs with capacitive transimpedance amplifier (CTIA) pixels are developed to enhance the imaging speed and sensitivity simultaneously. Novel column-parallel successive approximation register (SAR) ADCs are designed to reduce the area of column quantization circuits significantly.

A 1500 fps 256×256 CIS is designed in a 0.18-μm mixed-signal CMOS process for micro-CT. A tiny metal-oxide-metal (MOM) integration capacitor (C_INT) is used in the CTIA pixel to achieve the high sensitivity. To compensate the C_INT mismatches across the pixel array, an on-chip calibration scheme is developed. After calibration, a low fixed-pattern noise (FPN) of 0.52% can be achieved. With the white light illumination, the sensitivity is measured to be 68.5V/lux·s, which is higher than the previous highest CIS by 240%. The CIS also has low temporal noise (13.6e^-_rms). Its dynamic range is 56.5 dB. Minimum-size metal-insulator-metal (MIM) unit capacitors are used to implement the capacitor array of the SAR ADC. A digital calibration method based on dithering is devised to compensate the capacitor mismatches without any analog overhead. As a result, the size of a single SAR ADC is only 710×15 μm², which is the minimum among SAR ADCs with about 10-bit ENOB. After calibration, E̅N̅O̅B̅ is 9.83 bits at 768 kS/s.

The second CIS chip is designed in a 0.18-μm mixed-signal CMOS process for machine vision. It has a VGA (640×480) pixel array with a 1/2.5-inch optical format. It operates at 400 fps with 12-bit resolution. To achieve a higher spatial resolution, the CTIA pixel is redesigned with a small area (8.7×8.22 μm²), which is the smallest in the category. With new C_INT design using multi-layer MOM, the CIS achieves high sensitivity of 36.5 V/lux·s and low FPN of 0.55% without on-chip calibration. The sensitivity per pixel area is 67% higher than the first CIS design. A variable exposure time is enabled from 1/6000 s to 1/800 s. The CIS temporal noise is 15.6e^-_rms. The dynamic range is 50.1 dB. Small MOM unit capacitors are designed for the capacitor array of the SAR ADC to achieve both a small loading and small area. With simple MSB weights adjustments, E̅N̅O̅B̅ is 10.5 bits.