Short-range optical communications with data rates above 10 Gb/s have drawn significant research efforts in recent years as conventional copper cables have become less competitive with respect to weight, energy efficiency, limited channel bandwidth, crosstalk, and electromagnetic interference (EMI). Thus, complementary metal-oxide-semiconductor (CMOS) optoelectronic integrated circuits (OEICs) have become extremely attractive since they can be extensively adopted in short-range optical communications, such as local area networks (LANs), board-to-board interconnects, and data-to-data centers. In this thesis, two large OEIC systems are designed for different configurations. First of all, key challenges and bottlenecks of the two OEICs are discussed and analyzed from the system view...[ Read more ]

Short-range optical communications with data rates above 10 Gb/s have drawn significant research efforts in recent years as conventional copper cables have become less competitive with respect to weight, energy efficiency, limited channel bandwidth, crosstalk, and electromagnetic interference (EMI). Thus, complementary metal-oxide-semiconductor (CMOS) optoelectronic integrated circuits (OEICs) have become extremely attractive since they can be extensively adopted in short-range optical communications, such as local area networks (LANs), board-to-board interconnects, and data-to-data centers. In this thesis, two large OEIC systems are designed for different configurations. First of all, key challenges and bottlenecks of the two OEICs are discussed and analyzed from the system views. Second, different methodologies are presented to solve them. Third, fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) standard 1-V 65-nm CMOS technology, these two OEICs are designed, fabricated, and measured, respectively.

A 41-mW 30-Gb/s CMOS digitally-controlled OEIC with an off-chip 14-Gb/s Global Communication Semiconductors (GCS) PIN 850-nm photodetector (PD) is achieved with the proposed cascaded equalization approach. The presented OEIC consists of an inverter-based transimpedance amplifier (TIA), a DC offset cancellation (DOC) buffer, a main amplifier (MA), a 3-stage continuous-time linear equalizer (CTLE), a 2-stage limiting amplifier (LA), a DOC feedback loop, an on-chip low dropout (LDO) regulator, a 64-bit shift register, and a 50-Ω output driver (OD). The electrical measurement results demonstrate that it achieves the highest transimpedance gain (83 dBΩ) and the widest bandwidth (24 GHz) at the lowest power consumption (41 mW) among the CMOS OEICs published to date. The 3-stage CTLE offers 16-dB adjustable low-frequency gain to overcome channel loss and compensate for process, voltage and temperature (PVT) variations. Furthermore, the optical measurement results show that with a 30-Gb/s PD, the receiver achieves 10⁻¹² BER for 30-Gb/s, 2¹⁵−1 pseudo-random binary sequence (PRBS) inputs at −5.6-dBm sensitivity, and 1.37-pJ/bit efficiency. With a 14-Gb/s PD, the receiver can still reach 30 Gb/s at 10⁻¹² BER with only 0.6-dB degradation in sensitivity demonstrating the effectiveness of the proposed receiver design and the cascaded CTLE. With a 1/1.2-V voltage supply, the core area is 0.26 mm².

A 48-mW 18-Gb/s CMOS fully integrated OEIC with an on-chip PD and an adaptive cascaded equalization approach for 850-nm short-range optical communications provides a single-chip solution with many advantages compared with hybrid systems, such as low-cost, elimination of bonding and packaging at the key input node. However, CMOS on-chip PDs have characteristics of extremely limited bandwidth and much smaller responsivity, becoming the bottleneck of high-speed OEIC systems. To improve the limited bandwidth and responsivity performance of conventional CMOS on-chip PDs, a new PD topology is proposed, fabricated and measured. To extend the system’s overall bandwidth, a robust slow roll-up CTLE topology which compensates for both PVT variations and the lossy frequency response of the on-chip PD is proposed and designed. This OEIC consists of a CMOS P-well/Deep N-well (PW/DNW) on-chip PD, an inductive cascode inverter-based TIA, a DOC buffer, an MA, a 3-stage tunable CTLE, a 2-stage LA, a DOC feedback loop, an adaptive equalization loop (AEL), an on-chip LDO, and an output open-drain buffer (OB). The electrical measurement results show a transimpedance gain of 102 dBΩ and a bandwidth of 12.5 GHz at the power consumption of 48 mW. Furthermore, the optical measurement results demonstrate a fully integrated solution under (1) standard mode (0.5-V PD reverse bias voltage (V_PD)), a record data traffic of 9 Gb/s for 2¹⁵-1 PRBS with 10⁻¹² BER, −4.2-dBm optical input sensitivity, and 5.33-pJ/bit efficiency and (2) avalanche mode (12.3-V V_PD) another record data traffic of 18 Gb/s for 2¹⁵-1 PRBS with 10⁻¹² BER, −4.9-dBm optical input sensitivity, and 2.7-pJ/bit efficiency. With a 1/1.2-V voltage supply, the core area is 0.23 mm².