Low dropout regulators (LDRs) are indispensable power management functional blocks that provide supply voltages for noise-sensitive sub-blocks. This research focuses on the analysis and design of high-performance CMOS LDRs for power management applications.

First, a load-transient-enhanced and chip-area-efficient LDR based on a wide-swing voltage buffer without using on-chip compensation capacitor and large equivalent series resistance (ESR) for compensation is proposed. The small parasitic capacitor of the 1.2V PMOS buffer with small-sized power transistor guarantees low-ESR applications. The proposed LDR was fabricated in 0.13-μm mixed-mode CMOS process. The active chip area is 0.045mm² and the measured voltage dip is 10 mV for a 150mA load transient step with 30ns edge times...[ Read more ]

Low dropout regulators (LDRs) are indispensable power management functional blocks that provide supply voltages for noise-sensitive sub-blocks. This research focuses on the analysis and design of high-performance CMOS LDRs for power management applications.

First, a load-transient-enhanced and chip-area-efficient LDR based on a wide-swing voltage buffer without using on-chip compensation capacitor and large equivalent series resistance (ESR) for compensation is proposed. The small parasitic capacitor of the 1.2V PMOS buffer with small-sized power transistor guarantees low-ESR applications. The proposed LDR was fabricated in 0.13-μm mixed-mode CMOS process. The active chip area is 0.045mm² and the measured voltage dip is 10 mV for a 150mA load transient step with 30ns edge times.

Second, an LDR based on a matching-improved error amplifier is proposed that allows tighter load regulations. It also consists of an ultra-fast unity-gain buffer with a fast local loop that leads to significantly improved loop bandwidth and load transient responses. The LDR was implemented in 0.13um mixed-mode CMOS. The load-regulation is 25μV/mA. The quiescent current is 8μA and it achieves 6mV voltage dip for a load current step of 150mA with 30ns edge times.

Finally, a mixed-mode LDR based on a single-transistor-assisted ultra-fast voltage buffer is proposed for low-ESR or even zero-ESR applications. As the load current increases, the proposed buffer becomes a unity-gain buffer automatically to widen the gate voltage swing of the primary power transistor to achieve large load capability with compact chip area. A secondary power transistor provides large current to the load at heavy load, and enhances the load capability and load regulation. The proposed LDR was fabricated in a 0.13μm CMOS process. Measurement results show that it achieves 7.5mV voltage dip for a load current step of 150mA with 115ns edge times. The quiescent current is 6μA and the load regulation is 50μV/mA.