In the deep sub-micron process, the transistor intrinsic gain is low and the supply voltage is low, resulting in the great difficulty in designing a linear and high-gain operational transconductance amplifier (OTA) required by a pipelined ADC. The OTA and switched capacitors compose the multiplying-digital-to-analog converter (MDAC), which is the critical analog block in the pipelined ADC. Low-gain OTA and capacitor mismatch cause the real transfer function of the MDAC to be different from the ideal one, resulting in the poor overall ADC performance.

Therefore, a novel pipelined-ΣΔ ADC with interpolation-based nonlinear calibration is proposed in this thesis. First, the MDAC could be reconfigured into a 1st-order ΣΔ Modulator (SDM), which could be used as the accurate calibrati...[ Read more ]

In the deep sub-micron process, the transistor intrinsic gain is low and the supply voltage is low, resulting in the great difficulty in designing a linear and high-gain operational transconductance amplifier (OTA) required by a pipelined ADC. The OTA and switched capacitors compose the multiplying-digital-to-analog converter (MDAC), which is the critical analog block in the pipelined ADC. Low-gain OTA and capacitor mismatch cause the real transfer function of the MDAC to be different from the ideal one, resulting in the poor overall ADC performance.

Therefore, a novel pipelined-ΣΔ ADC with interpolation-based nonlinear calibration is proposed in this thesis. First, the MDAC could be reconfigured into a 1st-order ΣΔ Modulator (SDM), which could be used as the accurate calibration ADC. The reconfigured SOM could measure the real transfer function of the preceding MDAC. which would be stored and used for the code recovery in the normal pipelined ADC mode. Second, thanks to calibration, the OTA in the first MDAC could adopt the simplest and fastest single-stage common-source amplifier structure, the gain of which is only about 20 dB.

Without an additional dedicated calibration ADC, the proposed design totally avoids the requirement of a linear and high-gain OTA. The proposed ADC is implemented in a TSMC 65 nm 1.2 V CMOS process and verified by simulation results. Sampling at 300 MS/s, with a 1.2 V_pp 144.474 MHz sinusoidal input signal, the proposed ADC achieves the signal-to-noise-and-distortion ratio (SNDR) of 25.81 dB and 73.52 dB, before and after calibration respectively. After calibration, the spurious-free dynamic range (SFDR) is 79.90 dB and the effective-number-of-bits (ENOB) is 11.92 bit. The ADC core consumes the power of 638.82 mW and has a figure-of-merit (FOM) of 549.52 fJ/conv, while the complete chip consumes the power of 1566.04 mW and has an FOM of 1347.11 fJ/conv.