With the development of technology, the performance improve of processors cannot be achieved through feature size scaling alone. Multiple cores are integrated into a single processor to provide higher performance per energy and lower cost per function to applications. However, the power dissipation of the multi-core processors still keeps increasing, and becomes a critical criterion of the processor design. Power management supported by the power delivery system design has become a primary necessity to allow desired power shifting among different components for optimized overall performance by facilitating the low power techniques, e.g. power gating and dynamic voltage and frequency scaling (DVFS). However, those techniques induce design overhead of power delivery systems, in te...[ Read more ]

With the development of technology, the performance improve of processors cannot be achieved through feature size scaling alone. Multiple cores are integrated into a single processor to provide higher performance per energy and lower cost per function to applications. However, the power dissipation of the multi-core processors still keeps increasing, and becomes a critical criterion of the processor design. Power management supported by the power delivery system design has become a primary necessity to allow desired power shifting among different components for optimized overall performance by facilitating the low power techniques, e.g. power gating and dynamic voltage and frequency scaling (DVFS). However, those techniques induce design overhead of power delivery systems, in terms of hardware overhead, performance degradation, power integrity degradation, etc. Hence, in this dissertation, I systematically study the design concerns of efficient power delivery systems to decrease the system power consumption by better facilitating the low power techniques with the consideration of design overhead.

Power gating technique is widely utilized to reduce the static power of processors. However, it also introduces significant power/ground (P/G) noises in multi-core processors, and the traditional methods rely on reinforced circuits or fixed strategies to reduce the P/G noise with significant area, power and performance overheads. A hardware and software collaborated strategy is presented to provide efficient power gating. It consists of dynamic utilization of parasitic capacitance of on-chip caches to suppress the P/G during power gating at circuit level, and a control system to coordinate different components for victim protection and power gating aware scheduling at system level. The collaboration of circuit-level and system level design effort in the framework achieves considerable energy consumption reduction with slight execution time overhead for different applications and processors with different scales. Power gating is used to decrease the static power, while DVFS technique offers great promise to reduce the dynamic power consumption. Due to the DVFS limit of slow scaling speed, the employment of on-chip voltage regulators is able to improve the performance of DVFS by reducing its timescales. However, the on-chip voltage regulators will induce power loss, area consumption and increased susceptibility. An analysis and design optimization platform is proposed to effectively guide the power delivery system design, by combining an analytical model of the entire system for accurate and fast estimation of important characteristics and a convex-based design optimization strategy for efficient design space exploration. It automatically derives the design details of the power delivery system under customized design specs, and estimates its performance to explore the tradeoff of using on-chip voltage regulators. Besides, it is an increasingly difficult challenge to efficiently delivery necessary current to high-end processors, due to the conduction loss of power delivery network, especially power pins at the package. A chip pin constraint alleviation strategy through on/off-chip power delivery system co-design is proposed to effectively reduce the demand for power pins for continued computing performance growth. By combining the analytical model of power delivery system with the multi-core processor model of performance and memory bandwidth requirement, a design exploration framework of the entire system is built to evaluate the relationship between the chip pin constraint and system performance in multi-core processor scaling. The proposed strategy is able to achieve a significant pin count reduction to better support chip performance growth as technology scales.