The aggressively shrinking down of conventional CMOS transistor size has led to an impending power crisis, in which static power or leakage power consumption is the major concern. Many novel devices have been proposed to provide solutions for the power crisis in CMOSs. Among all the candidates TFET is considered as one of the most promising since it can avoid the fundamental limit of the subthreshold slope in the ET by using quantum interband tunneling instead of thermionic injection of electrons over the potential barrier. Moreover, TFET has the good compatibility with the current MOSFET platform. Theoretical studies and experimental demonstrations of TFETs have been reported in literature, however, most of these studies neglected the gate leakage current. As TFET based circuits mainly...[ Read more ]

The aggressively shrinking down of conventional CMOS transistor size has led to an impending power crisis, in which static power or leakage power consumption is the major concern. Many novel devices have been proposed to provide solutions for the power crisis in CMOSs. Among all the candidates TFET is considered as one of the most promising since it can avoid the fundamental limit of the subthreshold slope in the ET by using quantum interband tunneling instead of thermionic injection of electrons over the potential barrier. Moreover, TFET has the good compatibility with the current MOSFET platform. Theoretical studies and experimental demonstrations of TFETs have been reported in literature, however, most of these studies neglected the gate leakage current. As TFET based circuits mainly work in near-threshold region and gate leakage plays a crucial role in this region, it shouldn’t be neglected and requires more accurate modeling to evaluate its impact at circuit level. In addition, as low frequency noise is the limiting factor for analog circuits such as VCOs, mixers and PLLs, noise analysis is important for circuit designers to design low-noise TFET RF components. Many models for TFETS have been proposed in literature However, a compact model to enable gate leakage and noise analysis is still missing. This thesis is focused on the model development of gate leakage as well as low frequency noise in TFETs. Impact of gate leakage considerations on TFET circuit performance is evaluated as well.

An analytical model is presented on the basis of the understanding of the electron tunneling mechanism in a gate/insulator/silicon structure. The different effective gate lengths corresponding to operating conditions before saturation and after saturation are investigated. The validation of the model is verified by reproducing the TCAD simulation results with different device geometries. Afterwards, simulations based on the gate leakage model are carried out to evaluate the influence of gate leakage on circuit performance. Design constraints including noise margin, EDP and power consumption are studied. Results indicate that gate leakage has been underestimated before.In fact, gate leakage can substantially alter the subthreshold characteristics of TFETs. The results also highlight the necessity to apply new materials and techniques to minimize the gate leakage in TFETs to achieve better performance.Finally, the dependence of random telegraph signal amplitude on the trap locations is discussed using a TCAD simulator. Based on the understandings of the trapping-detrapping process in the device, a closed form solution of the low frequency noise is proposed, capturing the unique features of noise power spectral density in the TFET as well as reducing the computational complexity based on SPICE simulation considerations. Accuracy of the model is verified by experimental data reported in literature and circuit simulation is carriered out, showing the flexibility of the noise model.