In recent years, the worldwide market for image sensors has been growing rapidly and they are still in large demand, especially the CMOS image sensor for cellular devices. In this thesis, a column read-out circuit of an image sensor for cellular will be introduced. This read-out circuit was designed for a CIS with 8 M pixels, whose frame rate and exposure time are tunable.

This circuit contains a low noise variable gain amplifier (VGA), a 12 bit time interleave successive approximation (TI SAR) ADC with a novel calibration technique and a shift register. This read-out circuit is widely applicable in different situations (different illuminations). Both the noise and linearity performance were also taken into consideration for a better quality picture. The on chip calibration...[ Read more ]

In recent years, the worldwide market for image sensors has been growing rapidly and they are still in large demand, especially the CMOS image sensor for cellular devices. In this thesis, a column read-out circuit of an image sensor for cellular will be introduced. This read-out circuit was designed for a CIS with 8 M pixels, whose frame rate and exposure time are tunable.

This circuit contains a low noise variable gain amplifier (VGA), a 12 bit time interleave successive approximation (TI SAR) ADC with a novel calibration technique and a shift register. This read-out circuit is widely applicable in different situations (different illuminations). Both the noise and linearity performance were also taken into consideration for a better quality picture. The on chip calibration technique used in the ADC could effectively compensate the non-ideal factors, such as the parasitic capacitance on the top plat of the LSB section and the error of the bridge capacitor, which led to the weight mismatch between the MSB section and LSB section. Each single SAR could achieve a 10.2-bit ENOB at the sampling rate of 6.25 MS/s after calibration, while it could only achieve an 8.8-bit ENOB before calibration. At the same time, the technique needs little calibration overhead.

A power optimization is applied to this design in planning the pixel assignment for the higher power efficiency.

It is fabricated in a 65 nm 1P4M process. The size of this chip is about 30 mm².

The measurement result shows the proposed design was able to meet the requirement of a CIS for cellular devices. Some other works are also introduced in the end of this thesis.