THESIS
2016
xxiii, 149 pages : illustrations ; 30 cm
Abstract
In this thesis, design solutions are presented to improve the power efficiency and minimum operating voltage of on-die cache memories. A 44.2mW 3.2-GHz 3-port 1-kb register file that demonstrates measured operation from 1.2V down to 0.4V is presented. A
four-transistor read port is proposed for the design of low-capacitance dynamic bitlines. Switching power in the bitlines and the bitline precharge buffer is thereby reduced. The proposed read port is recommended for use in wide-worded register files that employ a wide dynamic-OR structure at the local bitline stage, and which operate in excess of 3-GHz. Robustness of the dynamic bitline is simultaneously enhanced by 58.8% as compared to the conventional low-V
t bitline in TSMC 65nm low-power low-V
t CMOS process.
Also proposed is an are...[
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In this thesis, design solutions are presented to improve the power efficiency and minimum operating voltage of on-die cache memories. A 44.2mW 3.2-GHz 3-port 1-kb register file that demonstrates measured operation from 1.2V down to 0.4V is presented. A
four-transistor read port is proposed for the design of low-capacitance dynamic bitlines. Switching power in the bitlines and the bitline precharge buffer is thereby reduced. The proposed read port is recommended for use in wide-worded register files that employ a wide dynamic-OR structure at the local bitline stage, and which operate in excess of 3-GHz. Robustness of the dynamic bitline is simultaneously enhanced by 58.8% as compared to the conventional low-V
t bitline in TSMC 65nm low-power low-V
t CMOS process.
Also proposed is an area-efficient 4-port register file for mobile application processors. A
compact bitcell is proposed that supports single-ended one-sided read operations using the direct read access mechanism, and single-ended write operations. Single-ended one-sided read operations help maintain sufficient bitcell data stability at 0.75V. Low active and standby power is achieved with the design of grounded write bitlines, a low-leakage-current bitcell,
and individual clock generators for top and bottom halves of the array. The proposed design, implemented in TSMC 65nm low-power dual-V
t CMOS process, achieves 17.8% reduction in silicon area, 19.6% lower active power, and 12.8% lower standby power when compared to the conventional dual-V
t register file.
Moving down to the next level of memory hierarchy, a supplementary write assist technique is proposed to eliminate PMOS-induced write failures in register file and Level-1 cache of low-voltage processors. The proposed scheme is recommended for use together with
supply voltage collapse write assist technique. A forward body bias is applied to bitcell PMOS transistors to ensure write completion within the active write cycle. Introduction of the proposed technique only slightly affects the hold data stability of non-accessed and half-selected bitcells. Measurement results from a 65nm test chip show a 2.3X improvement while a 15% reduction in bitcell hold data stability at 0.2V and 0.5V, respectively. Measured write delay is reduced by 52.5% and 64.3% at 0.2V and 0.3V, respectively.
The three most important V
MIN limiters of Level-2 and Level-3 cache, namely write ability, readability, and stability are simultaneously addressed to achieve a measured V
MIN of 0.21V for a 4kb 6T SRAM array. The improvement in V
MIN is achieved by ensuring write completion with the proposed supply voltage collapse with early charge-back write assist technique. A current-voltage latch-type sense amplifier is proposed to dynamically charge
back the non-evaluated bitline in a read operation in order to increase the developed bitline differential for reliable sensing. Data stability is dynamically enhanced with the introduction of forward body bias to bitcell PMOS transistors below 0.5V. The fabricated SRAM demonstrates measured read access frequency of 45kHz at 0.21V, with an active read power figure of 68.6nW, and a leakage power component of 29.5nW.
At the lowest end of operating voltage spectrum, a measured 140mV operation of a sub-threshold SRAM for implantable applications is presented. A differential read port is proposed to eliminate bitline leakage-induced read failures. The write bitline is floated to
achieve up to 37% reduction in column leakage currents. The array is implemented with wordline interleaving using a shared decoder to achieve 19% reduction in write wordline wire length and a 50% reduction in clock load within the write decoder. A hybrid sense amplifier
with a 55% lower bit error rate and reduced sensitivity to process variations is also proposed for robust differential read-out. Measurement results from a 65nm test chip confirm 13.1-kHz operation at 0.14V for a 1kb SRAM that consumes 28.1nW of leakage power and 30.5nW of total read power.
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