Nowadays, the clean and responsive power management circuits for system-on-a-chip (SoC) are demanding. The SoC enters idle mode by lowering the supply voltage, which even though can extend the battery lifetime, severely challenges the operation of all-analog circuits. As supply voltage reaches near-, even sub-threshold region, all-analog low dropout regulator (LDO) which powers the SoC will have a degraded performance.

The digital LDO (DLDO) emerges as a promising solution, by replacing the analog circuits with a wide-range-supply compatible digital controller and thus can realize fast response speed without compromising the power consumption. Nevertheless, there are remaining issues such as poor balance between speed and accuracy, and the sensitivity to process, voltage and temperatu...[ Read more ]

Nowadays, the clean and responsive power management circuits for system-on-a-chip (SoC) are demanding. The SoC enters idle mode by lowering the supply voltage, which even though can extend the battery lifetime, severely challenges the operation of all-analog circuits. As supply voltage reaches near-, even sub-threshold region, all-analog low dropout regulator (LDO) which powers the SoC will have a degraded performance.

The digital LDO (DLDO) emerges as a promising solution, by replacing the analog circuits with a wide-range-supply compatible digital controller and thus can realize fast response speed without compromising the power consumption. Nevertheless, there are remaining issues such as poor balance between speed and accuracy, and the sensitivity to process, voltage and temperature variations. In this thesis, circuit level innovations are conducted to overcome these limitations.

A capacitor-less DLDO is designed featuring a multi-step switching scheme, as well as an adaptive pipeline control with asynchronous clocking, for area- and power-efficient utilization. The measured load transient response is in nanoseconds for a 500 mA step at 0.6-1.0 V input. However, voltage ripple due to undesirable level toggling is observed during multi-step switching. The second prototype eliminates such ripples by adopting a soft multi-step switching technique which enables a more accurate regulation.

DLDOs tend to be more sensitive to the supply noise than their analog counterparts. Analog-assisted digital control is thus investigated to enhance the power supply rejection (PSR). As the auxiliary controller, an inverter-based amplifier (IBA) is designed with rail-to-rail common-mode operation and process-variation compensated trip-point control. The IBA-based LDO is designed, and achieves -20 dB PSR in the megahertz range at 0.2 V lowest supply voltage. This LDO pushes the limit of analog control, and is promising to assist the main regulator for PSR enhancement. All developed prototypes in this thesis are implemented using a standard 65-nm CMOS process.