Continuous technology scaling makes it possible to build processors with up to hundreds of processing units, or cores. Due to the large number of cores and the ever increasing computation requirements of emerging application workloads, power consumption has become a major concern in the design of modern multicore processors. For this reason, a lot of low-power techniques, such as power-gating and dynamic voltage-frequency scaling (DVFS), are developed and widely applied. To take fully advantage of these low-power control knobs, system-level power management is required to judiciously determine and schedule the power state for each functional unit. At the same time, technology scaling also introduces various sources of non-idealities, such as process variations and power supply noises....[ Read more ]

Continuous technology scaling makes it possible to build processors with up to hundreds of processing units, or cores. Due to the large number of cores and the ever increasing computation requirements of emerging application workloads, power consumption has become a major concern in the design of modern multicore processors. For this reason, a lot of low-power techniques, such as power-gating and dynamic voltage-frequency scaling (DVFS), are developed and widely applied. To take fully advantage of these low-power control knobs, system-level power management is required to judiciously determine and schedule the power state for each functional unit. At the same time, technology scaling also introduces various sources of non-idealities, such as process variations and power supply noises. In addition, the increasingly complex real-world applications impose challenges and runtime uncertainties for the underlying computing systems. Therefore an efficient and robust power manager must consider the impact of imperfections and variabilities that come from the environment, the hardware and the running workloads. For this end, in this dissertation, I investigate different design concerns in system-level power management for multicore processors, and propose several self-adaptive runtime power management approaches to improve the system energy-efficiency in a reliable and efficient way.

Power gating is one of the most effective techniques to reduce leakage power in multicore systems. However, the power-mode transition during power-gating of an individual processing unit (PU) will introduce serious power/ground (P/G) noise to the neighboring PUs. As technology scales, the P/G noise problem becomes a severe reliability threat to system power integrity. At the same time, the increasing degree of manufacturing process variation also brings uncertainties to the P/G noise problem and make it difficult to predict and mitigate. To tackle this problem, we analyze the characteristics of power-gating-induced P/G noise in the presence of process variation, and propose a hardware-software collaborated runtime approach to adaptively protect PUs from P/G noise. The proposed adaptive method achieves a comparable reliability to the most conservative static method while incurring much lower performance and energy overhead. Power-gating is used to reduce static power, while DVFS has been widely employed in commercial multicore systems to reduce dynamic power consumption and improve energy-efficiency for processors. Due to the complexity of emerging applications and the large number of cores, it is difficult to efficiently find a globally optimized voltage/frequency assignment at runtime. On-line learning based algorithms show great potential in dynamic power management with adaptation to runtime uncertainties and system behavior patterns. However, applying such method to multicore systems suffers from either a exponentially increasing amount of computation overhead or a loss of decision quality. To address this problem, a modular reinforcement learning based online DVFS control scheme is developed to make the system able to adaptively select globally optimized operating points with incurring only reasonably polynomial overhead to the core count. As aforementioned, the behaviors of application workloads play an important role in multicore system design, so I systematically characterize the behaviors of a set of real applications, and developed a formal model to accurately capture their computation and communication requirements. The analysis results provide useful knowledge for system-level energy-efficient multicore design. Based on the application modeling methodology, a real-world application based multicore benchmark suite and Network-on-Chip traffic suite are developed and publicly released to facilitate early-stage design exploration and evaluation of multicore systems.