The continuous scaling of integrated circuit technology is challenging the Cu interconnect’s physical limit. The resistivity of Cu increases rapidly due to scattering, leading to a large signal transmission delay. Furthermore, the increasing current density makes Cu interconnects unreliable due to electromigration. Carbon nanotubes (CNTs) are a promising alternative for vertical interconnects (vias) owing to their high current density capacity, electrical/thermal conductivity and high aspect ratios.

We developed CMOS-compatible CNT synthesis approaches on Ti silicide and Ni silicide substrates. A multilayer (Ni/Al/Ni) catalyst design was proposed to enhance nanoparticle formation by suppressing the diffusion of Ni into silicide and sintering of the Ni nanoparticles. Owing to th...[ Read more ]

The continuous scaling of integrated circuit technology is challenging the Cu interconnect’s physical limit. The resistivity of Cu increases rapidly due to scattering, leading to a large signal transmission delay. Furthermore, the increasing current density makes Cu interconnects unreliable due to electromigration. Carbon nanotubes (CNTs) are a promising alternative for vertical interconnects (vias) owing to their high current density capacity, electrical/thermal conductivity and high aspect ratios.

We developed CMOS-compatible CNT synthesis approaches on Ti silicide and Ni silicide substrates. A multilayer (Ni/Al/Ni) catalyst design was proposed to enhance nanoparticle formation by suppressing the diffusion of Ni into silicide and sintering of the Ni nanoparticles. Owing to the stable, high-density and evenly distributed nanoparticle catalysts with the multilayer catalyst design, we have synthesized vertically aligned multiwall CNTs (MWCNTs) with a wall density of 5.2 X 10¹² cm^-2. The proposed catalyst design enables CNT synthesis at temperatures as low as 350°C.

We developed a CNT via integration technology. To effectively preserve the surface properties of CNT tips and thus reduce the contact resistance of the CNT via, an integration process combining selective CNT growth and O₂ plasma-assisted post-CNT treatment was explored. A low CNT via resistance of 1.08 X 10^-6Ωcm² is obtained by preserving the CNT’s surface properties, enabling inner walls of MWCNTs for parallel current conduction and eliminating the side-wall CNT growth.

The scalability of CNT via technology is studied through the fabrication of sub-100 nm CNT vias on Ni silicide and investigation on the scaling trend. The preliminary integration of submicron CNT vias with silicided Si transistors suggests the functionality of the transistor after integration. The CMOS-compatible CNT via technology developed in this thesis is a step forward towards the application of CNT interconnects in CMOS technology.