Sensing anything (sense-worthy), anywhere and anytime is one of the future goals of Semiconductor industry. Combine it with Internet of Things (IOT) and there we go - ubiquitous deployment of smart sensors, preferably operating with passive energy sources like energy harvesting. Minimizing the power consumption of such systems is critical to ensure longer lifetime which leads to lower deployment costs and broad applications spectrum. Arguably, the most power hungry block in the sensing chain is the front end (instrumentation) amplifier which usually has to meet stringent noise and linearity constraints. This inevitably leads to high power consumption which is usually benchmarked with noise -efficiency factor (NEF).

In this work, we present a systematic design methodology which expl...[ Read more ]

Sensing anything (sense-worthy), anywhere and anytime is one of the future goals of Semiconductor industry. Combine it with Internet of Things (IOT) and there we go - ubiquitous deployment of smart sensors, preferably operating with passive energy sources like energy harvesting. Minimizing the power consumption of such systems is critical to ensure longer lifetime which leads to lower deployment costs and broad applications spectrum. Arguably, the most power hungry block in the sensing chain is the front end (instrumentation) amplifier which usually has to meet stringent noise and linearity constraints. This inevitably leads to high power consumption which is usually benchmarked with noise -efficiency factor (NEF).

In this work, we present a systematic design methodology which explores the design space (for ultra-low noise chopper instrumentation amplifiers) in all regions of MOSFET operation. Our work is the first of its kind to extend the g_m/I_D based design methodology for precision instrumentation amplifiers by taking into account a comprehensive set of parameters and validate the same through experimental demonstration. Various design tradeoffs, including the choice of chopping frequency for minimum residue offset and chopping ripple, gain-precision, bandwidth and area constraints are considered to meet the stringent specifications of a high-performance instrumentation amplifier with minimum power consumption and achieve state-of-the-art NEF.

We also design several readout interfaces for the MEMS-CMOS flow sensing platform. First, an integrated MEMS-CMOS flow sensor is presented which demonstrates a very compact system on chip (SoC) that can sense N₂ gas flow ranging from 0 to 26m/s (0-50sccm). The measured sensitivity of our MEMS-CMOS flow sensor is 35mV/sccm. Second, we design a nested-chopped CFIA by employing two sets of choppers; the outer chopper is clocked at a high frequency to mitigate the flicker noise whereas the inner chopper is clocked at the slower frequency to suppress the residue offset. Thus a CFIA with extremely-low offset (250nV) is obtained, which is interfaced with a pulse width modulation (PWM) based ADC to convert the flow-rate in digital bits. Third, a fully-differential version of this CFIA (with improved noise performance), that serves as a front-end IA to a 12-bit incremental ADC is also reported.

To conclude, several readout interfaces for fully-integrated CMOS-MEMS flow sensing platform have been implemented which enable a compact low-power flow sensor with enhanced dynamic range and minimum detectable flow value. The power consumption and design complexity of the high-performance readout interface are reduced by adopting mixed-signal integrated circuit techniques and a systematic design methodology.