Radio-frequency (RF) power amplifiers (PA) are top power consuming components, especially with today’s 4G communication enabled by long term evolution (LTE) technology. To improve the PA’s efficiency, dynamic power supply technologies, such as average power
tracking (APT), envelope tracking (ET) and envelope elimination and restoration (EER) have been proposed. In APT systems, the supply modulator adjusts the supply voltage according to the average power of the signal, similar to fast-dynamic-voltage-scaling (DVS) for digital circuits. For ET and EER, the supply modulator tracks the instantaneous changes in the envelope, thus the bandwidth of the tracking signal increases significantly. ET and EER supply modulators usually adopt a hybrid topology of a switching amplifier assisted by a...[
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Radio-frequency (RF) power amplifiers (PA) are top power consuming components, especially with today’s 4G communication enabled by long term evolution (LTE) technology. To improve the PA’s efficiency, dynamic power supply technologies, such as average power
tracking (APT), envelope tracking (ET) and envelope elimination and restoration (EER) have been proposed. In APT systems, the supply modulator adjusts the supply voltage according to the average power of the signal, similar to fast-dynamic-voltage-scaling (DVS) for digital circuits. For ET and EER, the supply modulator tracks the instantaneous changes in the envelope, thus the bandwidth of the tracking signal increases significantly. ET and EER supply modulators usually adopt a hybrid topology of a switching amplifier assisted by a linear amplifier to tradeoff between efficiency and bandwidth. High-frequency 3-level
switching converters are good candidates for the APT application and very suitable to be the switching amplifier in the hybrid topology due to the advantages of high efficiency, small ripple and fast tracking speed.
This thesis first presents a systematic analysis of integrated 3-level buck converters under both ideal and real conditions as a guidance for designing robust and fast 3-level buck converters. Under ideal conditions, the voltage conversion ratio, output voltage ripple and, in particular, the system’s loop-gain function are derived. Design considerations for real circuitry implementations of an integrated 3-level converter, such as the implementation of the flying capacitor, the impacts of the parasitic capacitors of the flying capacitor and the 4 power switches, and the time mismatch between the 2 duty-cycle signals are thoroughly discussed. Under these conditions, the voltage conversion ratio, the voltage across the flying
capacitor and the power efficiency are analyzed and verified with Cadence simulation results. The loop-gain function of an integrated 3-level buck converter with parasitic capacitors and time mismatch is derived with the state-space averaging method. The derived loop-gain
functions are verified with time-domain small signal injection simulation and measurement, with a good match between the analytical and experimental results.
After the systematic analysis, a 50-MHz 5-V-input 3-W-output 3-level buck converter prototype is presented. A real-time flying capacitor (C
F) calibration is proposed to ensure a constant voltage of V
g/2 across C
F, which is highly dependent on various practical conditions, such as parasitic capacitance, time mismatches or any loading circuits from C
F. The calibration is essential to ensure the reliability and minimize the inductor current and output voltage ripple, thus maintaining the advantages of the 3-level operation and further extending the system bandwidth without encountering sub-harmonic oscillation. The converter is
fabricated in a UMC 65-nm process using standard 2.5-V I/O devices, and is able to handle a 5-V input voltage and provide a 0.6 – 4.2 V-wide output range. In the measurement, the voltage across C
F is always calibrated to V
g/2 under various conditions to release the voltage stress on the high- and low-side power transistors and C
F, and to ensure reliability with up to 69% output voltage ripple reduction. A 90% peak efficiency and a 23–29 ns/V reference tracking response are also observed.
With the successful implementation of the 3-level buck converter, an AC-coupling supply modulator of a 25-MHz 3-level switching amplifier assisted by a wide-bandwidth linear amplifier is implemented for a fully-integrated CMOS PA for LTE applications. A multi-loop control is designed to fasten the switching amplifier speed, thus improving the overall efficiency. A high-frequency path is proposed to extend the bandwidth of the supply modulator from 33.9 MHz to 69.2 MHz without additional current consumption. The supply modulator is fabricated in a UMC 65-nm process with standard 1.2-V devices to achieve a 0.5-V − 2.5-V output voltage from a 2.4-V input voltage. The supply modulator measures
88.7% efficiency tracking a LTE-20MHz 16-QAM envelope. The multi-loop control improves the efficiency by up to 4%.
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