All electronic systems have inherent noise sources and a certain percentage of energy radiating from the system. The distorted differential signal in a communication link generates an unwanted common-mode (CM) component more severely at the backplane connector at twice the Nyquist frequency or at data rate frequency and harmonics (F_dr). The CM components are eventually radiated by the PCB parasitic antennas and degrade electromagnetic compatibility (EMC) performance. Regulatory bodies, for instance the Federal Communication Commission (FCC) and International Special Committee on Radio Interference (CISPR), prescribe a limit to control maximum radiation. It is therefore essential for systems-on-chip (SOCs) with high-performance digital large-scale integration (LSI) and RF/analog...[ Read more ]

All electronic systems have inherent noise sources and a certain percentage of energy radiating from the system. The distorted differential signal in a communication link generates an unwanted common-mode (CM) component more severely at the backplane connector at twice the Nyquist frequency or at data rate frequency and harmonics (F_dr). The CM components are eventually radiated by the PCB parasitic antennas and degrade electromagnetic compatibility (EMC) performance. Regulatory bodies, for instance the Federal Communication Commission (FCC) and International Special Committee on Radio Interference (CISPR), prescribe a limit to control maximum radiation. It is therefore essential for systems-on-chip (SOCs) with high-performance digital large-scale integration (LSI) and RF/analog circuits to have less electromagnetic radiation and to minimize electromagnetic interference (EMI) inside active devices. Meeting these guidelines becomes more challenging at high speed, as higher frequencies radiate more efficiently through small openings. Therefore, EMI is a challenging issue for packaging and PCB design at high speed. The EMI issue usually comes up late in the system, around the developmental stage, and requires a costly solution that is difficult to implement. Therefore, it is essential to counter the EMI issue during the product design phase instead of handling it at the end of product development. In this thesis, EMI-related common-mode noise is investigated in three stages: (1) identification of CM noise sources, (2) analysis and prediction of CM noise of the output driver and parallel I/Os and (3) suppression of CM noise.

In the first stage, the predominant source of CM noise is identified by a simplified communication link model, which only considers the non-idealities of the signal source and passive link. The signal source is an output of a high-speed serializer/deserializer (SERDES) transmitter (Tx), and the passive link is comprised of packaging and PCB interconnections. The CM voltage spectrum profile is categorized into two types of distortions, namely, linear distortion and non-linear distortion. The linear distortion is produced by skew, loading and amplitude mismatch between P/N channels, whereas the rising/falling edge mismatch is categorized as non-linear distortion since it produces a large power component at F_dr, causing a radiation issue and degrading the EMC performance. Analysis reveals that the non-linear active circuit predominantly produces the asymmetric rise and fall time of the output signal and is an intrinsic source responsible for generating the CM noise.

In the second stage, we present a novel methodology to systematically analyze and predict the CM noise of an output driver from various dependent parameters, including CMOS process corners, input signal, power supply and passive interconnections. Comprehensive analysis and prediction of EMI-related CM noise for a 20-Gb/s output driver in a 65-nm CMOS process is presented. Due to the NMOS-PMOS configuration in the push-pull driver, CM noise level variations are aggravated under process corners. The process corner variations can increase the CM noise up to 7.6x from a baseline level, a far greater impact than that of the other parameters. The EMI issue grows in complexity as the data rate per lane and the number of parallel lines continue to grow rapidly. Due to the high integration density, the CM noise can become a serious issue and can result in an inablility to meet FCC’s code of regulations.

Finally, we present the CM noise suppression of 20-Gb/s parallel I/Os using an on-chip slew-rate controller circuit in a 65-nm CMOS process. The critical step in controlling the CM noise is at the source, rather than improving the matching of passive interconnections. The CM noise issue is effectively circumvented by producing a matched slew-rate. The proposed arhcituecture balances the pull-up and pull-down network of ouput driver results in 20% increase in symmetry of rising and falling edge and reduce the peak CM noise by 5.4x. The calibrated output driver-produced matched slew-rate, besides providing a CM noise improvement, also helps in achieving better signal quality by increasing the vertical eye opening by 18 mV. Circuit design guidelines to control CM noise from the signal source during the design stage are also presented.