In recent years, the increasing demand for ultra-high-definition complementary metal-oxide-semiconductor (CMOS) image sensors (UHD-CISs), as well as a very high image quality for these sensors is the result of expanding application areas such as driver assistance systems, smartphones, robot guidance and security surveillance. The resolution of a UHD-CIS in such applications is up to 33M pixels for 8K video quality, causing the UHD-CIS to generate a signal more of than a Giga-bit per second. Therefore, UHD-CIS systems require high-speed data links in device-to-device communication interfaces. However, existing wireless communication cannot meet this increased data rate. To address this problem, this study aims to develop an optical wireless communication receiver for high-throughp...[ Read more ]

In recent years, the increasing demand for ultra-high-definition complementary metal-oxide-semiconductor (CMOS) image sensors (UHD-CISs), as well as a very high image quality for these sensors is the result of expanding application areas such as driver assistance systems, smartphones, robot guidance and security surveillance. The resolution of a UHD-CIS in such applications is up to 33M pixels for 8K video quality, causing the UHD-CIS to generate a signal more of than a Giga-bit per second. Therefore, UHD-CIS systems require high-speed data links in device-to-device communication interfaces. However, existing wireless communication cannot meet this increased data rate. To address this problem, this study aims to develop an optical wireless communication receiver for high-throughput sensory applications. The receiver consists of a receiver analog front end and a digital based clock and data recovery (CDR).

Firstly, an 1 – 8 Gb/s optical wireless communication receiver analog front end with a configurable transimpedance amplifier is designed in a 65 nm CMOS process. The configurable transimpedance amplifier has two operation modes to accommodate optical wireless environments. The proposed receiver in high-sensitivity mode is designed for long distance data transmission, whereas the receiver in high-speed data mode is designed for short range high speed communication. A noise optimization scheme of the receiver for optical wireless communication is also presented in this thesis. The noise power of the proposed receiver is optimized in both operation modes. Noise performance of the noise-optimized transimpedance amplifier is theoretically three times smaller than that of a conventional 1^st-order transimpedance amplifier. The receiver achieves 60 ??_??? input current noise at 1 Gb/s in high-sensitivity mode and 0.9 ??_??? input current noise at 8 Gb/s in high-speed data mode.

In the second part of this thesis, a CDR fabricated in a 65 nm CMOS process is designed for the optical wireless communication receiver to extract the timing information from the output of the analog front end. It is a 2 Gb/s – 8 Gb/s phase interpolator CDR with burst-mode multi-bit phase detection. The proposed technique accelerates the phase acquisition by compensating for the initial phase error. The phase acquisition time can be less than 16 UI. Therefore, the proposed design allows burst operation and is ready for multi-channel applications with the jitter of a recovered clock of 6.8 ??_??? at 2 Gb/s and 3 ??_??? at 8 Gb/s.