Low-dropout (LDO) regulators play a very important role in the power management integrated circuit (PMIC) family. They are often used as the final stage of a multi-step power conversion system, regulating the output voltage that is directly fed to the load circuit. Digital LDOs are compact and easy to implement because of their fully turned-on power transistors and compatibility with the standard digital design flow. Thus, they are usually integrated fully on chip and located close to the load circuits for point-of-load regulation, providing a high-quality output voltage. The key issue about digital LDOs is the power supply noise rejection capability which is required for the LDO to suppress the switching noises from the previous inductor-based switching converters or capacitor-based ch...[ Read more ]

Low-dropout (LDO) regulators play a very important role in the power management integrated circuit (PMIC) family. They are often used as the final stage of a multi-step power conversion system, regulating the output voltage that is directly fed to the load circuit. Digital LDOs are compact and easy to implement because of their fully turned-on power transistors and compatibility with the standard digital design flow. Thus, they are usually integrated fully on chip and located close to the load circuits for point-of-load regulation, providing a high-quality output voltage. The key issue about digital LDOs is the power supply noise rejection capability which is required for the LDO to suppress the switching noises from the previous inductor-based switching converters or capacitor-based charge pumps. This research will be focused on the development and implementation of effective hybrid LDO architectures targeted for improving the power supply noise rejection capability.

In the first part of this thesis, a digitally assisted analog hybrid architecture is proposed, combining the advantages from analog LDO architecture and digital LDO architecture. The digitally assisted analog LDO (DA-ALDO) can integrate the advantages of tight regulation and wide load current range from the analog control scheme with the merits of area-efficient power transistor utilization and fast transient speed from the digital control scheme. The prototype is verified in a 65-nm CMOS process and achieves 30 μV/mA load regulation and an FoM as low as 0.0073 ps.

The second part of this thesis presents a transfer function analysis of the power supply rejection ratio (PSRR) of conventional LDOs. An efficient and accurate model is proposed to facilitate the analysis, and the transfer function, along with the poles and zeros, is derived based on the simplified model. Software simulation results and numerical plots are both demonstrated and compared to verify the analytical results, with respect to two specific design examples. The proposed model and the analytical results serve as the theoretical foundation of the design of high-PSRR LDOs.

In the third part of this thesis, a digitally assisted analog retention mode LDO is proposed with improved PSRR performance. Based on the conclusions from the previous two parts, in retention mode the LDO provides superior regulation with a small quiescent current. The degraded PSRR performance poses no significant threat because the LDO only delivers a small current to the load. In non-retention mode, the proposed LDO exhibits good full-spectrum PSRR performance at both large and small load current levels, and at least –28.3 dB PSRR performance is available across full spectrum at maximum load current.