Wide-bandgap (WBG) semiconductors, GaN and SiC based power devices have been regarded as promising candidates for next-generation power switches in numerous power electronics applications owning to their capabilities to deliver low ON-resistance (R_ON), fast switching speed, and high-temperature operation. Many efforts have been devoted to commercializing the GaN and SiC based power devices, as witnessed by the emergence of several products released by industrial start-ups as well as leading power semiconductor manufacturers. To help designers to get the most out of GaN and SiC power devices and maximize the system-level benefits, this thesis focuses on application-relevant characterization and implementation of GaN and SiC based power switching transistors for their adoption in high-pe...[ Read more ]

Wide-bandgap (WBG) semiconductors, GaN and SiC based power devices have been regarded as promising candidates for next-generation power switches in numerous power electronics applications owning to their capabilities to deliver low ON-resistance (R_ON), fast switching speed, and high-temperature operation. Many efforts have been devoted to commercializing the GaN and SiC based power devices, as witnessed by the emergence of several products released by industrial start-ups as well as leading power semiconductor manufacturers. To help designers to get the most out of GaN and SiC power devices and maximize the system-level benefits, this thesis focuses on application-relevant characterization and implementation of GaN and SiC based power switching transistors for their adoption in high-performance power converters.

Firstly, a critical yet seldom studied device dynamic behavior: dynamic OFF-state leakage current (I_OFF) in p-GaN gate high-electron-mobility transistors (HEMTs) is investigated. Systematic characteristics, physical mechanisms, empirical model, and the corresponding suppression strategy of dynamic I_OFF are comprehensively studied. It is found that the I_OFF under dynamic pulse-mode is much higher than the I_OFF obtained in the quasi-static measurement, and is further enhanced with ON-state hole injection through the gate. The underlying physical mechanisms are explained by the dynamic behavior of the traps in the buffer layer. Under continuous switching waveforms, saturation of dynamic I_OFF is observed due to a balanced trapping/de-trapping process of buffer traps. The saturated value of dynamic I_OFF is influenced by various switching conditions, such as measurement delay time, duty cycle, switching frequency, gate drive voltage and temperature. A physics-based empirical model of dynamic I_OFF is established, providing an accurate estimation of OFF-state power consumption (E_OFF) for various switching conditions. To suppress the high dynamic I_OFF and lower the E_OFF in practical power switching applications, a sufficiently large negative OFF-state gate bias could be recommended in the gate driver turn-off voltage design for the p-GaN gate HEMTs.

Secondly, an all-WBG GaN/SiC cascode power device is proposed by combining the merits of high channel mobility in lateral GaN heterojunctions and high voltage blocking capability in vertical SiC structures. The all-WBG GaN/SiC cascode device is consisted of an enhancement-mode (E-mode) low-voltage p-GaN gate HEMT as control device and a depletion-mode (D-mode) high-voltage SiC junction field-effect transistor (JFET) as voltage blocking device. Systematic characterizations of the GaN/SiC cascode device are presented. Compared with the exiting commercial WBG semiconductor power device technologies, the demonstrated 1200-V/100-mΩ GaN/SiC cascode device simultaneously features many benefits including small terminal capacitances, avalanche breakdown capability, thermally stable threshold voltage (V_TH), negligible dynamic RON degradation, and small gate charge (Q_G). An adequately low OFF-state middle point voltage (V_M) across the low-voltage GaN device is achieved for its safe operation under both the static and dynamic switching conditions. In board-level characterization, a custom-designed double-pulse test circuit is built to evaluate the transient switching performance. Optimal gate drive conditions are proposed to 1) overcome the drain bias induced positive dynamic V_TH shift; and 2) suppress the increased dynamic I_OFF induced by ON-state hole injection. Fast transient switching speed and stable high-temperature switching performance are realized, indicating its potential for high-frequency and high-temperature power switching applications.

Thirdly, the corresponding dv/dt-control methods of the 1200-V/100-mΩ GaN/SiC cascode device are studied. A controllable dv/dt-control method of the high-frequency power device switching transients could help minimize electromagnetic interference (EMI) noise and reduce conduction/emission aspects in certain applications. A novel dv/dt-control technology based on a resistor-capacitor-diode (RCD) circuit is proposed to compare with other conventional control methods. The effectiveness of the dv/dt-control methods is evaluated using a double-pulse test circuit with an inductive load and the underlying control mechanisms are discussed. The proposed method could achieve a more effective control over the cascode’s dv/dt-rates owing to its balanced control on the transient turn-on/turn-off behaviors and not enhance the drain-to-gate coupling effect. As a result, problems like layout caused over-voltages, earth leakage currents, or EMI problems in general could be handled, facilitating the utilization of the GaN/SiC cascode power switch in a wide range of applications.