It is well known that the carbon nanotube (CNT) intrinsically has superior axial thermal conductivity. In the past, many research efforts attempted to apply CNT in electronic packaging to enhance the thermal performance of devices or modules. Nevertheless, even after three decades of CNT, researchers have still not been able to implement meaningful applications of CNT in the packaging of microelectronics. This study proposes an innovative approach to make use of the superior axial thermal conductivity of CNT for heat conduction, in particular, for the thermal management applications in 3D stacked Integrated Circuits (IC) packaging.

In this study, two substrates are bonded together with a fixed gap in between. This configuration forms two parallel surfaces. Subsequently, two large areas...[ Read more ]

It is well known that the carbon nanotube (CNT) intrinsically has superior axial thermal conductivity. In the past, many research efforts attempted to apply CNT in electronic packaging to enhance the thermal performance of devices or modules. Nevertheless, even after three decades of CNT, researchers have still not been able to implement meaningful applications of CNT in the packaging of microelectronics. This study proposes an innovative approach to make use of the superior axial thermal conductivity of CNT for heat conduction, in particular, for the thermal management applications in 3D stacked Integrated Circuits (IC) packaging.

In this study, two substrates are bonded together with a fixed gap in between. This configuration forms two parallel surfaces. Subsequently, two large areas of CNT forests are grown simultaneously from the two parallel surfaces into each other. This face-to-face fabrication brings CNTs from the two sides into contact and eventually they become interlaced. The interlaced CNTs provide better mechanical contacts and even allow some CNTs from two sides to fuse together. These phenomena enhance the heat conduction between the two parallel surfaces. The configuration of parallel surfaces with a fixed gap happens to be the actual situation of 3D stacked chips.

To observe the interlacing of CNTs between parallel surfaces, we applied the double side dicing technology, which not only achieved a clear cross-section, but also improved the yield of dicing higher than 90%. To overcome the micrometer level misalignment between the diced substrates, we used DC biased plasma etching to expose CNT-CNT interface with the top substrate as the self-aligned mask and to measure the real joint depth. To study the properties of CNT-CNT interlacing, we applied unbiased plasma etching to distinct interlaced CNTs and the fused bunches of CNTs.

In order to measure the thermal properties of CNTs, we invented the double side exposed packaging structure to allow infrared monitoring of the heater during the static heating of the sample with current flow and bottom temperature controlled with T3Ster. In comparison with the CNT-CNT interface formed by pressing, the novel structure can achieve 5 times smaller thermal resistance. It is foreseeable that the outcome of this research may lead to a revolution in the thermal management of 3D stacked IC packaging.