High-precision and moderate-speed analog-to-digital converters (ADCs) are in great demand for analog front-end circuits, such as medical imaging, instrumentation and circuit testing. This thesis focuses on designing high-precision successive-approximation-register (SAR) ADCs in power-efficient ways.

A new asynchronous least-significant-bit (LSB) averaging technique is presented to improve the signal-to-noise ratio (SNR) of high-precision SAR ADCs with high power efficiency. After normal conversion, a linear searching is performed to coarsely reduce the conversion error asynchronously. Subsequently, the comparator performs a complementary number of comparisons with unchanged residue voltages to further reduce the error. Compared to statistical noise reduction methods, the proposed metho...[ Read more ]

High-precision and moderate-speed analog-to-digital converters (ADCs) are in great demand for analog front-end circuits, such as medical imaging, instrumentation and circuit testing. This thesis focuses on designing high-precision successive-approximation-register (SAR) ADCs in power-efficient ways.

A new asynchronous least-significant-bit (LSB) averaging technique is presented to improve the signal-to-noise ratio (SNR) of high-precision SAR ADCs with high power efficiency. After normal conversion, a linear searching is performed to coarsely reduce the conversion error asynchronously. Subsequently, the comparator performs a complementary number of comparisons with unchanged residue voltages to further reduce the error. Compared to statistical noise reduction methods, the proposed method is insensitive to process, voltage, and temperature (PVT) variations since it does not require knowledge of the noise distribution. Additionally, it only slightly reduces the signal bandwidth as only 10 extra cycles are required. Therefore, the proposed method is suitable for low-noise, high-resolution SAR ADCs with MS/s speed. The proposed technique is implemented on a 16-bit SAR ADC in a 180-nm CMOS process. Running at 1 MS/s with the proposed technique, the measured signal-to-noise-and-distortion ratio (SNDR) is improved from 91.8 dBFS to 95.1 dBFS, and the dynamic range (DR) is improved from 93.8 dB to 98.1 dB. With power increased by 6.2% and period increased by 11%, this technique leads to a 2.59 dB Schreier figure-of-merit (FoM_SNDR) and a 3.59 dB FoM_DR improvement. The ADC consumes 7.1 mW and achieves a 173.6-dB FoM_SNDR and a 176.6-dB FoM_DR, respectively.

A dual-core architecture for SAR ADC with power reduction scheme is also included as the research preview.