Analog-to-digital converters (ADCs) are fundamental and essential components in signal digitization for sensor systems. Among the various ADC architectures available, successive-approximation register (SAR) ADCs have become increasingly popular due to their high efficiency, simplicity, low latency, and scalability. While traditionally used for medium-speed and medium-precision applications, recent advancements in techniques such as redundancy, time-interleaving, and pipelining have enabled SAR ADCs to achieve high speed and high resolution with high efficiency, further expanding its application. This thesis focuses on the development of efficient high-resolution and high-speed SAR ADCs for medical imaging and Light Detection and Ranging (LiDAR) systems.

The first design presents an eff...[ Read more ]

Analog-to-digital converters (ADCs) are fundamental and essential components in signal digitization for sensor systems. Among the various ADC architectures available, successive-approximation register (SAR) ADCs have become increasingly popular due to their high efficiency, simplicity, low latency, and scalability. While traditionally used for medium-speed and medium-precision applications, recent advancements in techniques such as redundancy, time-interleaving, and pipelining have enabled SAR ADCs to achieve high speed and high resolution with high efficiency, further expanding its application. This thesis focuses on the development of efficient high-resolution and high-speed SAR ADCs for medical imaging and Light Detection and Ranging (LiDAR) systems.

The first design presents an efficient 8-MS/s 16-bit successive approximation register (SAR) analog-to-digital converter (ADC) for medical imaging sensors. Conventionally, improving the SAR ADC speed compromises the signal-to-noise-and-distortion ratio (SNDR) and energy efficiency due to the high precision requirement and the sequential bit-cycling. In this design, the proposed symmetric complementary switching (SCS) scheme reduces the parasitic capacitance in the sampling path and the settling error of the capacitive digital-to-analog converter (CDAC) with low SNDR and hardware penalties. In addition, to reduce reference ripples, active reference buffers generally consume high power while the passive methods may degrade the SNDR or occupy large areas. To efficiently reduce reference settling errors, an area-efficient split passive reference segmentation technique (SPRS) is developed, which suppresses the reference settling error through the split reference segmentation. The ADC is fabricated in a 180-nm CMOS process and occupies an area of 0.57 mm². The measurements show that the ADC achieves a peak SNDR of 89.2 dB at 8 MS/s with a power consumption of 9.5 mW, resulting in a Schreier-figure-of-merit (FoM) of 175.4 dB. The high linearity and low noise lead to a better image quality. The high sampling rate enables multiplexed digitization for a larger number of channels, improving the spatial resolution of medical imaging systems.

The second design presents a timing-skew-free time-interleaved (TI) successive-approximation register (SAR) analog-to-digital converter (ADC). By implementing an architecture with single sample-and-hold (S/H) network, this design eliminates the need of a costly timing-skew calibration. This approach offers significant hardware and power savings, making the design energy and area efficient, and suitable for applications that require multiple ADC channels. The prototype ADC is designed and fabricated in a 28-nm CMOS process, achieving a signal-to-noise-and-distortion ratio (SNDR) of 48.1 dB and a spurious free dynamic range (SFDR) of 58.4 dB with a Nyquist input, running at a speed of 1.4 GS/s. The ADC dissipates 24 mW, resulting in a Walden figure-of-merit (FoM) of 82.4 fJ/conv.-step, and occupies an active area of 0.06 mm². This design is suitable for the multi-channel high-performance LiDAR systems that demand tens of high-speed ADCs with high area-and power-efficiencies to improve long-range precision.