Modern GPU/CPU systems integrate hundreds of cores on a single die, and future scaling envisions even more cores being incorporated. However, this growth is constrained by the limited number of transistors per die. To address this challenge, chiplet technology has emerged as a promising approach due to its higher integration density, improved flexibility, and reduced cost. Nevertheless, existing chiplet interconnection technologies suffer from limitations in terms of bandwidth, latency, and energy efficiency. In contrast, optical interconnects offer significant advantages, including low latency, ultra-high bandwidth, and good energy efficiency, making them an ideal choice for high-performance chiplet-based systems. However, previously proposed optical networks lack scalability and are n...[ Read more ]

Modern GPU/CPU systems integrate hundreds of cores on a single die, and future scaling envisions even more cores being incorporated. However, this growth is constrained by the limited number of transistors per die. To address this challenge, chiplet technology has emerged as a promising approach due to its higher integration density, improved flexibility, and reduced cost. Nevertheless, existing chiplet interconnection technologies suffer from limitations in terms of bandwidth, latency, and energy efficiency. In contrast, optical interconnects offer significant advantages, including low latency, ultra-high bandwidth, and good energy efficiency, making them an ideal choice for high-performance chiplet-based systems. However, previously proposed optical networks lack scalability and are not directly applicable to existing chiplet-based systems. Moreover, they ignore the communication characteristics specific to CPU/GPU systems.

To address these issues comprehensively, we establish a power model and an optical device cost model for inter-chiplet optical interconnect. Additionally, we conduct a quantitative analysis of the traffic characteristics within chiplet-based CPU and GPU systems. Based on these findings, we introduce a photonic cache coherence network (PCCN) for chiplet-based manycore processors, which accelerates cache coherence transactions and alleviates cache coherence overhead. We propose a novel region-based optical network (RONet) with a tuning-free mechanism for chiplet-based GPU, which significantly enhances system performance and energy efficiency. Considering the limitation of RONet, we further optimize our design and propose a group-based optical network (GROOT), which is more scalable and resolves the NUMA issue in RONet.