The increasing demand for high-bandwidth and low-latency wireless communication in consumer electronics necessitates the development of efficient and cost-effective ultra-low power millimeter-wave power and information receivers. This thesis proposes a novel 28-GHz system architecture that leverages existing hardware for information reception, i.e., phased array antennas and beamformers, to enable far-field wireless power reception, minimizing cost overhead and performance loss. This is achieved through a unique rectifier-switch (RSW) block integrated within receive beamformers, enabling dual-mode operation for power and information reception.

The ultra-low-power 28-GHz four-channel receive beamformer incorporates an RSW with 29.7% peak efficiency, a three-stage low-noise amplifier (LN...[ Read more ]

The increasing demand for high-bandwidth and low-latency wireless communication in consumer electronics necessitates the development of efficient and cost-effective ultra-low power millimeter-wave power and information receivers. This thesis proposes a novel 28-GHz system architecture that leverages existing hardware for information reception, i.e., phased array antennas and beamformers, to enable far-field wireless power reception, minimizing cost overhead and performance loss. This is achieved through a unique rectifier-switch (RSW) block integrated within receive beamformers, enabling dual-mode operation for power and information reception.

The ultra-low-power 28-GHz four-channel receive beamformer incorporates an RSW with 29.7% peak efficiency, a three-stage low-noise amplifier (LNA), a 9-bit active variable gain phase shifter (VGPS), and a four-to-one Wilkinson power combiner (WPC) consumes 4.3 mW per channel, achieving 4.4 dB minimum noise figure, 22.2 dB power gain, 2.4 GHz bandwidth, and -24.1 dBm IIP3. The VGPS archives 0.5-degree and 0.1-dB resolutions in phase and gain control, respectively. All components are designed and post-layout simulated in 28nm CMOS technology.

Furthermore, this thesis introduces a cost-effective microstrip antenna design utilizing a dielectric loss reduction technique. By incorporating in-patch through-hole ground vias, the electric field within internal dielectric layers is suppressed, allowing the use of cost-effective FR-4 layers for power and digital signals for phased array systems. This approach also minimizes parasitic radiation from antenna probes, further enhancing performance. A prototype linearly polarized patch antenna with a peak realized gain of 5.2 dBi and impedance bandwidth of 7.8% is fabricated and measured, validating the proposed technique. The implementation of 1×2, 2×2, 2×4, and 4×4 arrays with a λ₀/2 element spacing demonstrates the effectiveness of the proposed antenna design for phased arrays.

This thesis contributes to the advancement of ultra-low power 28-GHz power and information receivers for consumer electronics, offering a cost-effective and efficient solution for next-generation wireless communication systems.