Active matrix liquid-crystal displays (LCD's) are gaining popularity as a replacement for classical cathode ray tube (CRT) displays due to their flatness, small size and light weight. Mainstream markets include workstations and high-definition television (HDTV). Poly-Si TFT's, having high carrier mobilities and being CMOS compatible, can potentially realize very large-area LCD's with integrated peripheral drive circuits. However, a key challenge is how to realize high quality poly-Si TFT's at low temperature (≤600°C) to avoid damaging the low-cost glass substrates used in LCD's. When processed at low temperature, TFT electrical performance tends to be degraded by small grain sizes, large trap densities, and rough surfaces....[ Read more ]

Active matrix liquid-crystal displays (LCD's) are gaining popularity as a replacement for classical cathode ray tube (CRT) displays due to their flatness, small size and light weight. Mainstream markets include workstations and high-definition television (HDTV). Poly-Si TFT's, having high carrier mobilities and being CMOS compatible, can potentially realize very large-area LCD's with integrated peripheral drive circuits. However, a key challenge is how to realize high quality poly-Si TFT's at low temperature (≤600°C) to avoid damaging the low-cost glass substrates used in LCD's. When processed at low temperature, TFT electrical performance tends to be degraded by small grain sizes, large trap densities, and rough surfaces.

In recent years, many researchers have used chemical-mechanical polishing (CMP) for a number of applications, varying from multilevel interconnect planarization to BESOI wafer fabrication, to achieve better planarity and uniformity. This work is motivated by the possibility of using CMP in active devices like TFT's. There are two different approaches to improve device performance by using polishing. The first approach, involving a 'touch' polish (TP) process which causes no significant stock removal, is considered to be effective in smoothing the surface of the active-layer film, thereby improving the poly-Si/SiO₂ interface. Clear correlation has been found between surface morphology and device performance. It can be combined with the use of hydrogenation to produce a high performance TFI. Transmission electron microscopy (TEM) and atomic force microscopy (AFM) have been studied to show unequivocal physical differences among the polished and unpolished films. The second approach involves a novel poly-Si grain-size enhancement technique which combines recrystallization of thick a-Si film and chemical- mechanical polishing. Significant enhancements in mobilities and on-currents have been observed without degradation in leakage current. This effect is more significant in small dimension TFT's as the enlarged grain size becomes comparable to the channel length.