This thesis presents the design of RF CMOS circuits required for integrated transceivers, including a downconversion mixer, an image-rejection upconversion mixer and a Q-enhanced LC bandpass filter....[ Read more ]

This thesis presents the design of RF CMOS circuits required for integrated transceivers, including a downconversion mixer, an image-rejection upconversion mixer and a Q-enhanced LC bandpass filter.

The downconversion mixer has a simple architecture consisting of a cross-coupled pair and two source-followers as the core. The mixing property is superior due to the characteristics of unbalanced source-coupled pairs. It is also insensitive to both device mismatches as well as body effect. Independence of the first two poles allows the input and output bandwidth to be optimized separately.

Both downconversion and upconversion mixers have been fabricated in a 0.8μm CMOS process. Experimentally, the downconversion mixer achieves an input bandwidth of 1 GHz at which IIP3 of 23.5 dBm is measured. Its conversion loss and 1-dB compression point are measured to be 4.4 dBm and 14.5 dBm, respectively. It occupies an active die area of 100 μm x 100 μm, and consumes 2.5 mW from a single 2.6 V supply.

The image-rejection upconversion mixer is formed by a parallel connection of two identical mixers which have a similar architecture as the downconversion one. The image-rejection property is a consequence of selectively canceling the signals in the unwanted sideband.

Within the input bandwidth of 600 MHz, the measured gain mismatches between individual channel is less than 1 dB with a conversion gain of -11 dB. At this frequency, the l-dB compression point is 11 dBm, and the IIP3 is 22.5 dBm. It dissipates 20 mW from a 3.3 V power supply. Its active area is 290 μm X 150 μm.

The classical LC bandpass filter is implemented in CMOS technology using lossy monolithic inductors. It has a fully differential structure with a tunable quality factor using negative resistances and a variable centre frequency based on Miller capacitances.

The filter's centre frequency can be varied from 820 MHz to 930 MHz with an adjustable Q-factor up to 880 in the post-simulation. The simulated peak conversion gain is 42 dB. The IIP3 is -38 dBm when the Q-factor is 650 and the centre frequency is 900 MHz. Its nominal supply voltage is 3 V with a current consumption of 40 mA, and it occupies an active area of 740 μm x 840 μm.