Turbo Codes, introduced by Berrou et al., achieve astonishingly good performance at a low signal-to-noise ratio (SNR). Unfortunately, due to the code structure, it is not practi-cal to implement the optimum decoding algorithm and thus, the performance of Turbo Codes is sensitive to the suboptimal decoding algorithms used....[ Read more ]

Turbo Codes, introduced by Berrou et al., achieve astonishingly good performance at a low signal-to-noise ratio (SNR). Unfortunately, due to the code structure, it is not practi-cal to implement the optimum decoding algorithm and thus, the performance of Turbo Codes is sensitive to the suboptimal decoding algorithms used.

In general, there are two classes of suboptimal algorithms for Turbo Code decoding, soft output Viterbi algorithm (SOVA) and maximum a-posteriori (MAP) algorithm. Though the former one is of lower complexity which makes it more suitable for hardware imple-mentation, it suffers serious performance degradation especially when the data frame is short in comparison with MAP. In this thesis, the reasons for the performance loss of SOVA are discussed. Based on our observations and analysis, we propose some simple modifications to improve the performance of SOVA. These modifications lead to decoder designs with nearly no additional hardware complexity.

Comparing with decoders for traditional convolutional codes, the iterative decoding scheme of the Turbo Code decoder consumes substantially large amount of power. Moreover, the decoding latency is enlarged by several times. Consequently, it is important to investigate low power SOVA decoder structures for Turbo Codes with small decoding latency. In this thesis, we also study two low power VLSI archtectures. It is found that the power consumption can be reduced while maintaining low decodinglatency and reasonable complexity.