The semiconductor industry nowadays competes by pursuing higher operating frequency and higher-function integration. These factors are the driving force behind the explosive growth of the semiconductor industry. However these components are, at the same time, the main factors contributing to the high power consumption. High power consumption means low operating hours, high packaging cost and low reliability. For portable video applications, power consumption is especially important because the multimedia functions need extensive computational power: In this thesis work, a hierarchical, mixed-level power estimation framework is built which can bridge the gap between the system and architectural level design. This power estimation framework is specially developed for designing low power p...[ Read more ]

The semiconductor industry nowadays competes by pursuing higher operating frequency and higher-function integration. These factors are the driving force behind the explosive growth of the semiconductor industry. However these components are, at the same time, the main factors contributing to the high power consumption. High power consumption means low operating hours, high packaging cost and low reliability. For portable video applications, power consumption is especially important because the multimedia functions need extensive computational power: In this thesis work, a hierarchical, mixed-level power estimation framework is built which can bridge the gap between the system and architectural level design. This power estimation framework is specially developed for designing low power portable video applications. It can perform fast and accurate Power-Area-Delay trade-off for multimedia applications, which in turns help shortening the VLSI design cycle. Within this power estimation framework, an architectural cycle-based power macro-model is employed to provide fast and accurate evaluation of the power consumption of different DSP applications. As its name implies, this power macro-model can produce cycle-by-cycle, as well as, the average power estimate. This power macro-model is an order of magnitude faster than the gate level power estimation while the accuracy is within 5% of that of the gate level counterpart. The training methodology and the detail training mechanism will be discussed. Using the power estimation framework and the cycle-based power macro-model, different motion estimation architectures used in the video encoder are investigated in the dimensions of power area and delay. Also, an energy efficient approach - variable bit truncation motion estimation, are also evaluated. It shows that, using the bit truncation motion estimation in the video compression, the power can be saved substantially (>70%) without scarifying much on the image quality.