In CDMA systems, the information data is spread into a wideband signal. This spreading allows the Rake receiver to achieve multipath diversity which significantly improve the performance under frequency selective fading channels. However, the Rake receiver needs to operate at a very high chip rate and multiple branches are needed to separate the signal arriving along different paths. Moreover, as CDMA systems are interference limited, instantaneous data rate varies according to the information source. Traditionally, the receiver determines the data rate by trying multiple decoders and picking the best match. As the forward error correcting codes used for CDMA systems typically require very complex decoders, this multiple decoding process also increases the complexity of the receiver. Ci...[ Read more ]

In CDMA systems, the information data is spread into a wideband signal. This spreading allows the Rake receiver to achieve multipath diversity which significantly improve the performance under frequency selective fading channels. However, the Rake receiver needs to operate at a very high chip rate and multiple branches are needed to separate the signal arriving along different paths. Moreover, as CDMA systems are interference limited, instantaneous data rate varies according to the information source. Traditionally, the receiver determines the data rate by trying multiple decoders and picking the best match. As the forward error correcting codes used for CDMA systems typically require very complex decoders, this multiple decoding process also increases the complexity of the receiver. Circuits with high complexity running at high rate consume fair amount of power and power is one of the most costly resources in mobile handset design.

In this thesis, we present a new Rake finger architecture and a pre-decoding rate determination algorithm to reduce the overall power consumption at the handset receiver. This is verified by counting the number of addition and multiplication operations needed per transmit symbol. As different operations run at different rates, the new architecture partitions the Rake receiver into the Rake "head", which is expected to be implemented by custom ASIC, and the Rake "tail" whose function can be easily achieved using a DSP chip. We also study the required precision of the A/D output (or the Rake receiver input) and the quantization effect of Rake "head" in our architecture. To avoid the multiple decoding process, we present two rate determination algorithms for the two rate sets specified in the IS-95 CDMA standard. Using these algorithms, the receiver just needs to decode the received frame at most twice, and mostly once, instead of four times as in the conventional method. We analyze the error rate performance of the system with and without the rate determination algorithm and estimated the overall saving in the power consumption achieved by our rate determination algorithm.