This dissertation describes the design of a CMOS 900-MHz bandpass amplifier that is suitable for RF transceivers. The work employs the state-of-art inductive degeneration techniques to minimize the noise figure and explores the use of lossy spiral inductors in high frequency circuit to realize input matching networks on-chip. A Q-compensation circuit is included to achieve a 25-MHz 3-dB bandwidth. Besides, a center frequency tuning circuit is also embedded to compensate for frequency deviations due to process variations....[ Read more ]

This dissertation describes the design of a CMOS 900-MHz bandpass amplifier that is suitable for RF transceivers. The work employs the state-of-art inductive degeneration techniques to minimize the noise figure and explores the use of lossy spiral inductors in high frequency circuit to realize input matching networks on-chip. A Q-compensation circuit is included to achieve a 25-MHz 3-dB bandwidth. Besides, a center frequency tuning circuit is also embedded to compensate for frequency deviations due to process variations.

In the first prototype, a second-order bandpass amplifier had been fabricated in standard 0.8 μm single-poly, triple-metal CMOS process (HP SCN26G) provided by MOSIS™. With a 3-V supply, at 950-MHz and a 3-dB bandwidth of 25-MHz, the measured voltage gain is 26 dB and the input S₁₁ is -13 dB. Under the same baising condition, the input third-order intermodulation product (IIP₃) and input-referred 1-dB compression point (P_0,1-dB) are -21.5 dBm and -3 1.5 dBm respectively. The image rejection at 140-MHz away from the desired signal is 20 dB. In addition, the Q of the amplifier can be tuned from around 2 to infinity and the center frequency can also be varied from 930 MHz to 1040 MHz. On the grounds that the measured on-chip spiral's quality factor is merely around 2 (compared to around 3 to 5 in recent literatures), the measured noise figure of the whole amplifier is around 10 dB. The power dissipation and the die area of the first prototype are 90 mW and 1.2 mm x 0.8 mm respectively.

So as to enhance the image rejection ability and to reduce the power consumption, a sixth-order bandpass amplifier had been implemented and fabricated in standard 0.5μm CMOS process using 2-V supply. In this second prototype, a bandpass amplifier was cascaded with two identical second-order bandpass filters to realize the sixth-order bandpass response.

For the bandpass amplifier in the second prototype, the measured voltage gain is 26 dB at 832 MHz and a S₁₁ of -14 dB. With an overall 3-dB bandwidth of 25MHz, the measured IIP₃ and the 1-dB compression point of the bandpass amplifier are -18.5 dBm and -29 dBm respectively. Besides, the center frequency can be varied between 760 MHz and 832 MHz. The measured noise figure is 9.6 dB, which is much higher than the simulation due to inadequate modeling of the thermal noise in short-channel MOSFETs and the use of low-quality inductors.

Meanwhile, the performance of the three-stage design in the second prototype was tested, the measured center frequency of the design is located at 830 MHz with a gain of 16 dB. The corresponding 3-dB bandwidth is 25 MHz and the image rejection at 140 MHz away from the desired signal is around 45 dB. In addition, the input third-order intermodulation product (IIP₃) and the input-referred 1 -dB compression point are -15 dBm and -26 dBm respectively. The total current consumption of the three-stage design is 90 mA and the die area of the circuit is only 1.2 mm x 0.8 mm as two-layer inductors were utilized in the design.