Recent rapid development of non-volatile memory and high density SRAM has called for the need of high quality dielectric on polysilicon. The high quality dielectric can improve the performance of TFT on SRAM as well as reliability of EEPROM. Dielectric on polysilicon substrate exhibits inferior properties compared with that grown on bulk Silicon or SOI. One of the major causes is the surface roughness of polysilicon film. By reducing the surface roughness of the polysilicon film, dielectric and TFT with improved properties can be realized....[ Read more ]

Recent rapid development of non-volatile memory and high density SRAM has called for the need of high quality dielectric on polysilicon. The high quality dielectric can improve the performance of TFT on SRAM as well as reliability of EEPROM. Dielectric on polysilicon substrate exhibits inferior properties compared with that grown on bulk Silicon or SOI. One of the major causes is the surface roughness of polysilicon film. By reducing the surface roughness of the polysilicon film, dielectric and TFT with improved properties can be realized.

Two methods were proposed to improve the dielectric quality, the first one begin Chemical-Mechanical Polish (CMP) and the second one Metal-Induced-Lateral- Crystallization (MILC). Under Atomic Force Microscopy (AFM), it is founded that the polysilicon film with either of CMP or MILC treatment possesses surface with reduced surface roughness when compared with polysilicon film without any treatment.

It is found that on the planarized polysilicon film, dielectric can exhibit higher breakdown E-field, lower charge trapping rate, lower tunneling current density and higher charge to breakdown value. TFT on planarized polysilicon exhibits increased carrier mobility, steeper sub-threshold slope and reduced threshold voltage.