In recent years, there has been significant research and development effort for Third-generation or 3G wireless and mobile communication systems. Such systems will be able to provide end-user with data rates of up to 384 kbps for wide area coverage and up to 2 Mbps for local area coverage. This will also significantly expand the range of options available to users and allow communication, information, multimedia and entertainment service to be delivered via wireless terminals. Of the various services, Code Division Multiple Access (CDMA) has been regarded as an important part of the third generation systems because of its high frequency utilization and suitability for handling multimedia communication....[ Read more ]

In recent years, there has been significant research and development effort for Third-generation or 3G wireless and mobile communication systems. Such systems will be able to provide end-user with data rates of up to 384 kbps for wide area coverage and up to 2 Mbps for local area coverage. This will also significantly expand the range of options available to users and allow communication, information, multimedia and entertainment service to be delivered via wireless terminals. Of the various services, Code Division Multiple Access (CDMA) has been regarded as an important part of the third generation systems because of its high frequency utilization and suitability for handling multimedia communication.

The performance of Wideband Code Division Multiple Access (WCDMA) will be severely degraded with the number of users increases due to the increase in interference. To improve the system capacity, multi-user detection which cancel the interference generated by other users can be used. Recently a Joint Successive Interference Cancellation with Interleaving (JSICI) scheme [1] has been proposed for multi-user detection. However the complexity of the scheme is very high. In this thesis, we propose a low complexity VLSI architecture which can implement this JSICI scheme for asynchronous frame time transmission efficiently in VLSI. Effective memory architecture, low complexity hardware sharing and low power techniques were proposed. To improve the performance of the asynchronous frame time transmission, a novel delay scheduling mechanism is proposed. Simulation results show that the performance is close to that of the synchronous time frame case.