With the increasing demand of wireless portable, what we want is a low voltage, low power, small area and low cost devices. Recently, most of the published papers demonstrated the possibility of CMOS receiver for wireless communication. However, in most cases, these receivers consume a lot of power under a high supply voltage (2.7 V) to maintain a good performance. With the technology scales down, supply voltage has to be decrease at the same time to prevent device breakage. This, on the other hand, introduces a lot of difficulty in low voltage design....[ Read more ]

With the increasing demand of wireless portable, what we want is a low voltage, low power, small area and low cost devices. Recently, most of the published papers demonstrated the possibility of CMOS receiver for wireless communication. However, in most cases, these receivers consume a lot of power under a high supply voltage (>2.7 V) to maintain a good performance. With the technology scales down, supply voltage has to be decrease at the same time to prevent device breakage. This, on the other hand, introduces a lot of difficulty in low voltage design.

In this thesis, we are going to demonstrate the possibility of designing low voltage, low power CMOS frontend for Bluetooth application. Two frontend designs that make use of on-chip inductors and off-chip inductors are presented for comparison. Both designs are realized in 0.35μm CMOS technology. The first design is a LNA with source degeneration image rejection filter with the use of on-chip inductors. In this design, we propose a new technique that can solve the problem of the previous design in terms of minimum supply voltage, noise and linearity simultaneously. Measurement result shows that, under a single 1-V supply with a proposed IF of 110MHz and center frequency of 2.25 GHz, the LNA has a gain of 12 dB, Noise Figure of 5.1 dB, image rejection ratio of over 50 dB, IIP₃ of 1 dBm while drawing a current of 3.6mA.

The second design is a frontend for Bluetooth receiver including LNA, Mixer, Antialiasing filter and Polyphase Filter. Since the goal of this design is ultra low power consumption, so off-chip inductors are used to minimize the power consumption and noise for a given Voltage Gain, IIP₃ under a 1-V supply. Simulation results show a total Voltage gain of 27 dB, Noise Figure of 6.8 dB, IIP₃ of -3.9 dBm while drawing a total current of 1.5mA for the whole Frontend receiver.