For switched-capacitor (SC) circuits, power consumption is proportional to the number of the opamps used. In a classical filter design, two opamps are needed to realize a second-order biquadratic filter. Double-sampling pseudo-2-path technique can be used to implement a simple second-order biquadratic filter (resonator) with only one opamp. However, since no damping capacitor exits, such a double-sampling pseudo-2-path technique cannot be used to implement a wide-band SC filter....[ Read more ]

For switched-capacitor (SC) circuits, power consumption is proportional to the number of the opamps used. In a classical filter design, two opamps are needed to realize a second-order biquadratic filter. Double-sampling pseudo-2-path technique can be used to implement a simple second-order biquadratic filter (resonator) with only one opamp. However, since no damping capacitor exits, such a double-sampling pseudo-2-path technique cannot be used to implement a wide-band SC filter.

On the other hand, demand for high data-rate integrated circuits has rapidly grown due to the technological development in many applications, such as WCDMA and WLAN. Signal bandwidths of these applications are from several MHz to several ten MHz. For low IF systems, the quality factor of the channel-selection bandpass filter becomes very low. At the same time, the filter needs to have sharp transition from passband to stopband in order to provide enough attenuation for adjacent channel signals, which cannot still be achievable with conventional low-Q SC bandpass filters.

In this project, two wide-band SC filters are designed. The first design aims at low-power and high-frequency filters for video applications. The second design focuses on achieving high roll-off for low-Q filter applications. Both designs are realized in a 0.35-μm CMOS process with V_tp=0.80V and V_tn=0.65V.

In the first project, a modified double-sampling pesudo-2-path technique has been proposed to implement a fully differential 3-V 44-MHz wideband bandpass filter. Using only three opamps, the filter implements a 6^th-order bandpass response with a center frequency of 44MHz and a bandwidth of 6.28MHz (Q=7) with an effective sampling frequency of 176MHz. A 3-step variable gain is designed with each step being 6dB. The dynamic range is measured to be 57.3dB (@ 3% IM3), and the IIP3 is measured to be 27dBm at a voltage gain of -3dB. The proposed filter consumes a power of 92.5mW and an active chip area of 950um X 510um.

In the second project, a high roll-off wide-band SC bandpass filter employing a double-sampling technique is proposed. The post-simulation results show the proposed design achieves a 10-MHz center frequency with a bandwidth of 2.5MHz. The attenuation at 2.5-MHz away from the center frequency is larger than 35dB while consuming a total power of 99mW and a chip area of 2000um X 1000um. The fabrication of the filter is in progress.