THESIS
2002
89 leaves : ill. ; 30 cm
Abstract
As the feature sizes of MOSFETs are scaled down to the deep sub-tenth micron regime, ultra-shallow source/drain extensions as well as heavily doped pockets are required to suppress the short-channel effects. However, these structures result in high series resistance and parasitic capacitance that offset the performance gain achieved through scaling. To optimise the performance of future sub-tenth micron applications, a better source/drain engineered structure is necessary....[
Read more ]
As the feature sizes of MOSFETs are scaled down to the deep sub-tenth micron regime, ultra-shallow source/drain extensions as well as heavily doped pockets are required to suppress the short-channel effects. However, these structures result in high series resistance and parasitic capacitance that offset the performance gain achieved through scaling. To optimise the performance of future sub-tenth micron applications, a better source/drain engineered structure is necessary.
In this thesis, a novel MOSFETs source/drain structure to simultaneously reduce the series resistance and parasitic capacitance with the diffusion region on top of an insulating oxide trenches is proposed. The idea is to form a smaller opening, through which the elevated source/drain diffusion regions are connected to the shallow source/drain extension.
In this thesis, we present an preliminary series resistance and parasitic capacitance model, and in so doing describe the features of the novel CMOS structure which include an elevated source/drain, an ultrashallower source drain extension (SDE) junction with higher doping concentration, a silicide-diffusion contact system and tin sidewall length. The performance of the proposed SDOI structure was studied using a 2-D device simulator (MEDICI and HSpice), and various parasitic components resulting from the new structure were modeled. Compared with that of the conventional planner source/drain structure, the reduction of parasitic capacitance and series resistance can be as much as 80% and 30% respectively. The improvement in device performance can result in more than a 25% lower inverter delay in 0.18 μm CMOS technology. Finally, the issues on the technological feasibility of the proposed SDOI MOSFETs, including the key steps such as the restricted source/drain junction regions and the elevated poly source/drain, are discussed. A feasible process flow with fully CMOS compatible technology is provided. Furthermore, the proposed process flow feasibility is successfully verified with the 2-D process simulation tool-Tsuprem4.
Post a Comment