The RF industry has experienced an explosive growth in the past few years. As a result, high-performance RF architectures are urgently needed to satisfy the market. To fulfill the task, improvements must be achieved at all levels: from technology, circuit schematic to physical layout strategy. Several design options for each level are discussed in this thesis....[ Read more ]

The RF industry has experienced an explosive growth in the past few years. As a result, high-performance RF architectures are urgently needed to satisfy the market. To fulfill the task, improvements must be achieved at all levels: from technology, circuit schematic to physical layout strategy. Several design options for each level are discussed in this thesis.

SiGe BiCMOS and SOI CMOS technology are two promising candidates for the mainstream integrated circuit technology. Bipolar transistors in the SiGe BiCMOS process can achieve higher transconductance value and better noise performance compared to MOSFETs in standard CMOS technology. The SOI CMOS process significantly reduces the device parasitics, and enables improvements in power gain and noise performance. Taking low noise amplifier (LNA) and voltage-controlled oscillator (VCO) as examples, circuit simulation is performed to compare the two technologies to standard CMOS technology in terms of RF applications.

Compact waffle layout is proposed and compared to traditional multifinger layout in standard CMOS technology. The parasitic elements of the MOSFET are carefully studied and verified with simulation and experimental results in the two layout strategies. By exploiting compact waffle MOSFET, transistor active area, drain/source diffusion area can be reduced by 30% and 25% respectively, compared to multifinger MOSFET. The maximum frequency of oscillation f_max is also improved compared to the optimal value in multifinger layout strategy. With the reduced device parasitic elements, circuit simulation of LNA, VCO and passive mixer is performed to demonstrate the performance improvement in RF applications.

Finally, an oscillator with active inductor tuning is compared to the generic LC-tank VCO. A very wide tuning range and significant chip area reduction can be achieved with some compromising in phase noise. A design guideline is given to minimize the phase noise of the active inductor tuning oscillator (AITO).