Over the last decade, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) has been reduced continuously, and it is predicted to be as small as 65 nm in year 2007 according to the Semiconductor Industry Association’s roadmap. Such small channel lengths enable the implementation of high-speed and sophisticated systems on a single chip. Nevertheless, the small channel length requires a low power-supply voltage. With the future development of system-on-a-chip (SoC), it will push the integrated analog circuitries to be driven by low supply-voltage. This ultimately causes the implementation of high frequency circuits to be tougher and the performance is unavoidably degraded. It motivates the research focusing on low voltage high frequency circuits' implementatio...[ Read more ]

Over the last decade, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) has been reduced continuously, and it is predicted to be as small as 65 nm in year 2007 according to the Semiconductor Industry Association’s roadmap. Such small channel lengths enable the implementation of high-speed and sophisticated systems on a single chip. Nevertheless, the small channel length requires a low power-supply voltage. With the future development of system-on-a-chip (SoC), it will push the integrated analog circuitries to be driven by low supply-voltage. This ultimately causes the implementation of high frequency circuits to be tougher and the performance is unavoidably degraded. It motivates the research focusing on low voltage high frequency circuits' implementation.

In this thesis, two high-speed low voltage systems have been designed and demonstrated. Both designs are realized in 0.18-μm CMOS technology. The first one is a 1-V 2.5-GHz double-rate Phase-Locked Loop with zero clock skew for microprocessor application. A novel phase-alignment technique is proposed to achieve an inherent zero delay between the input reference and the output. Operated with the input and output frequencies of 1.25-GHz and 2.50-GHz, respectively, and with a 1-V supply voltage, the PLL prototype measures a rms jitter of 1.3 ps and a peak-to-peak jitter of 8.1 ps while consuming 13 mW and occupying a chip area of 2.5 mm².

The second design is a 1-V 5.2-GHz CMOS frequency synthesizer for WLAN IEEE 802.11a. A novel design technique is proposed to achieve a 1-V 5.2-GHz low-power programmable frequency divider for the synthesizer. At a 1-V supply, the synthesizer measures a phase noise of -136 dBc/Hz at a 20-MHz frequency offset and a spurious tone of less than -80 dBc while dissipating 27.5 mW and occupying a total core area of 1.03 mm².