The success of Turbo codes pushes the system performance close to the Shannon limit and the iterative decoding algorithm used in turbo-decoding attracts a lot of research interest in recent years. To reduce the decoding delay, several decoding algorithm based on different graphic models are proposed: a class of iterative decoding algorithm based on the Tanner graph or its extension; an iterative decoding algorithm as a belief propagation over the Bayesian network; sum product algorithm over factor graph. Very recently, Mow proposed a new graphic model, hypertrellis, which generalizes both the trellis and the factor graph. The hypertrellis can overcome the inefficiency of Tanner graph in representing non-binary codes. The connectivity of hypertrellis facilitates the visualization of the...[ Read more ]

The success of Turbo codes pushes the system performance close to the Shannon limit and the iterative decoding algorithm used in turbo-decoding attracts a lot of research interest in recent years. To reduce the decoding delay, several decoding algorithm based on different graphic models are proposed: a class of iterative decoding algorithm based on the Tanner graph or its extension; an iterative decoding algorithm as a belief propagation over the Bayesian network; sum product algorithm over factor graph. Very recently, Mow proposed a new graphic model, hypertrellis, which generalizes both the trellis and the factor graph. The hypertrellis can overcome the inefficiency of Tanner graph in representing non-binary codes. The connectivity of hypertrellis facilitates the visualization of the code structure at the codeword level, which is not available in factor graph. Furthermore, a fully parallel iterative decoding (FPID) algorithm based on hypertrellis can achieve a very high degree of parallelism to reduce the decoding delay.

Channel decoders are traditionally implemented in digital VLSI to achieve sufficient numerical accuracy, as well as to make full use of powerful and mature design tools. Recent researchers have shown that analog VLSI implementation of decoders is an attractive approach for high speed applications, like magnetic reading and equalization. In addition, analog decoders could achieve better power and area efficiency than digital decoders could.

In this thesis, we discussed the analog integrated circuit implementation of hypertrellis decoders with FPID and proposed a system structure with inherent 2-stage pipeline to enhance speed as well as testability. A quaternary single check (5, 4) hypertrellis analog decoder is designed to demonstrate those proposed ideas. Computation is performed at 50M symbol per second in cascode current mode signal processing efficient routing, accuracy and speed. The decoder occupies an area of 1.9 mm*2.0 mm and consumes a total power of 50 mW.