Abstract
Currently the fast table lookup has become a major bottleneck of the router performance. When a packet arrives, the port processor performs an IP lookup in its routing table to determine the next hop of the packet by its destination address. The main challenges lie in the time needed for longest prefix matching for each incoming IP packet. Updating the table is another hurdle to overcome for RAM-based approaches.

In this thesis, we proposed a RAM-based architecture for IP lookup. The design requirements are the following: one memory access per lookup, reasonable amount of memory requirement, and fast table updates. We show the design and its performance in the thesis.