Recent interests in the wireless RF transceivers have been focused on high levels of integration and adaptability to support multiple communication standards. Programmable digital channel select filtering is resorted to adapt and integrate different standards into a single-chip multimode transceiver as to reduce the overall cost. A high dynamic range delta-sigma analog-to-digital converter (ΔΣ ADC) with multimode capability is therefore required to digitize the desired signal in the presence of strong adjacent channel interference to adapt a wide range of dynamic range and signal bandwidth requirements for different standards. To further enhance the flexibility, depending on the surrounding interference, part of the channel select filtering can be performed in analog domain. As such, it...[ Read more ]

Recent interests in the wireless RF transceivers have been focused on high levels of integration and adaptability to support multiple communication standards. Programmable digital channel select filtering is resorted to adapt and integrate different standards into a single-chip multimode transceiver as to reduce the overall cost. A high dynamic range delta-sigma analog-to-digital converter (ΔΣ ADC) with multimode capability is therefore required to digitize the desired signal in the presence of strong adjacent channel interference to adapt a wide range of dynamic range and signal bandwidth requirements for different standards. To further enhance the flexibility, depending on the surrounding interference, part of the channel select filtering can be performed in analog domain. As such, it lowers the dynamic range requirement of ΔΣ ADC and allows the potential feasibility of an adaptable power reduction strategy.

This thesis describes a multimode cascade 2-1-1 ΔΣ ADC for UHF RFID reader at both architectural and circuit levels. Adaptable power reduction strategy is introduced to meet the multiple-protocol requirements in both dynamic range and signal bandwidth. An experimental prototype was designed and fabricated in a 0.18-μm CMOS process with an active area of 1.5mm². The achievable dynamic range at 16X and 24X oversampling ratio are 67dB and 72dB within the entire signal bandwidth varying from 80kHz to 1.28MHz with the total power consumption ranging from 3.7mW to 19.9mW from a 1.8V supply, respectively.